Reliability of Cu pillar on substrate interconnects in high performance flip chip packages

2011 ◽  
Author(s):  
Rajesh Katkar ◽  
Michael Huynh ◽  
Laura Mirkarimi
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Cu Pillar

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002404-002423
Author(s):  
Rajesh Katkar ◽  
Michael Huynh ◽  
Laura Mirkarimi
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Failure Process ◽  
Form Factors ◽  
Cycle Performance ◽  
High Yield ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Electromigration Lifetime ◽  
Low K

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

Development of Plating Process for Micro Bump Formation

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000751-000777
Author(s):  
Takuma Katase ◽  
Koji Tatsumi ◽  
Tekeshi Hatta ◽  
Masayuki Ishikawa ◽  
Akihiro Masuda
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Solder Bump ◽  
Small Diameter ◽  
Lead Free ◽  
Current Status ◽  
Bump Height ◽  
Cu Pillar ◽  
Key Technologies ◽  
Connection Length

Flip chip connection has been applied to a lot of applications in order to shorten the connection length of high performance devices. Solder bumping is one of the key technologies for flip chip connections, and its quality makes a large impact on the reliability after packaging. Recently, bump size has been getting smaller to correspond to the finer connection pitch, and these types of bumps are called “micro bumps”. Electroplating is one of the methods for solder bump formation. Sn-Ag is considered as the best candidate for lead free alloy to be used for the electroplating method. Electroplating is a suitable method to form micro bumps. For micro bump connections, Cu pillar is necessary to obtain a suitable bump height. Traditionally, there have been some technical difficulties to achieve smooth morphology on “micro bump” surfaces due to its small diameter and/or high aspect ratio. Lately, we succeeded in developing a new Sn-Ag plating process for micro bump formation by optimizing the plating process. We also successfully developed our Cu plating process for Cu pillar application with a high plating rate more than 10 ASD condition. Our Cu plating process is available to obtain various surface shapes of Cu pillar such as flat, dome, and concave. In this study, we established our plating process with Cu pillar + Sn-Ag solder cap. We will review our current status and features of our plating chemical for micro bump formation.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

High-performance semiconductor optical amplifier array for self-aligned packaging using Si V-groove flip-chip technique

1995 ◽  
Vol 7 (5) ◽  
pp. 476-478 ◽  
Author(s):  
D. Leclerc ◽  
P. Brosson ◽  
F. Pommereau ◽  
R. Ngo ◽  
P. Doussiere ◽  
...  
Keyword(s):  
Semiconductor Optical Amplifier ◽  
High Performance ◽  
Flip Chip ◽  
Optical Amplifier
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