Fine Pitch Cu Pillar with Bond on Lead (BOL) Assembly Challenges for Low Cost and High Performance Flip Chip Package

2017 ◽  
Author(s):  
Nokibul Islam ◽  
Vinayak Pandey ◽  
KyungOe Kim
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Cu Pillar ◽  
Fine Pitch

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002404-002423
Author(s):  
Rajesh Katkar ◽  
Michael Huynh ◽  
Laura Mirkarimi
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Failure Process ◽  
Form Factors ◽  
Cycle Performance ◽  
High Yield ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Electromigration Lifetime ◽  
Low K

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Control of Bump Morphology in Lead Free Solder Plating for Higher Density Packaging

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001643-001669
Author(s):  
Koji Tatsumi ◽  
Kyouhei Mineo ◽  
Takeshi Hatta ◽  
Takuma Katase ◽  
Masayuki Ishikawa ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
Short Circuit ◽  
Lead Free Solder ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Different Shapes ◽  
Free Solder ◽  
High Density Packaging

Solder bumping is one of the key technologies for flip chip connection. Flip chip connection has been moving forward to its further downsizing and higher integration with new technologies, such as Cu pillar, micro bump and Through Silicon Via (TSV). Unlike some methods like solder printing and ball mounting, electroplating is a very promising technology for upcoming finer bump formation. We have been developing SnAg plating chemical while taking technology progress and customers' needs into consideration at the same time. Today, we see more variety of requests including for high speed plating to increase the productivity and also for high density packaging such as narrowing the bump pitch itself and downsizing of the bump diameter. To meet these technical needs, some adjustments of plating chemical will be necessary. This time we developed new plating chemicals to correspond to bump miniaturization. For instance, our new SnAg chemical can control bump morphology while maintaining the high deposition speed. With our new plating chemicals, we can deposit mushroom bumps that grow vertically against the resist surface, also this new chemicals work effectively to prevent short-circuit between mushroom bumps with fine pitch from forming. In addition, we succeeded in developing high speed Cu pillar plating chemicals that can control the surface morphology to create different shapes. We'd like to present our updates on controlling bump morphology for various applications.

Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

Effect of preformed IMC Layer on Electromigration of Solder Capped Cu Pillar Bump Interconnection on an organic substrate

2012 ◽  
Vol 2012 (1) ◽  
pp. 000455-000463 ◽  
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Flip Chip ◽  
Organic Substrate ◽  
Stress Tests ◽  
Cross Sectional ◽  
Current Stress ◽  
Barrier Layers ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Cu Pillar Bump ◽  
Cu Dissolution

The electromigration behavior of 80 μm pitch solder capped Cu pillar bump interconnection on an organic carrier is studied and discussed. Recently the solder capped Cu pillar bump technology has been widely used in mobile applications as a peripheral ultra fine pitch flip chip interconnection technique. The solder capped Cu pillar bumps are formed on Al pads which are commonly used in wirebonding technique. It allows us an easy control of the space between the die and the substrate simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. Solder capped Cu pillar bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with a no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. It is an ideal technology for the systems requiring fine pitch structures. In 2011, the EM tests were performed on 80 μm pitch solder capped Cu pillar bump interconnections and the effects of Ni barrier layers on the Cu pillars and the preformed intermetallic compound (IMC) layers on the EM tests were studied. The EM test conditions of the test vehicles were 7–10 kA/cm2 at 125–170°C. The Cu pillar height was 45 μm and the solder height was 25 μm. The solder composition was Sn-2.5Ag. Aged condition for pre-formed IMCs was 2,000 hours at 150°C. It was shown that the formation of the pre-formed IMC layers and the insertion of Ni barrier layers are effective in reducing the Cu atoms dissolution. In this report, it is studied that which of the IMC layers, Cu3Sn or Cu6Sn5, is more effective in preventing the Cu atom dissolution. The cross-sectional analyses of the joints after the 2000 hours of the test with 7kA/cm2 at 170°C were performed for this purpose. The relationship between the thickness of Cu3Sn IMC layer and the Cu migration is also studied by performing the current stress tests on the joints with controlled Cu3Sn IMC thicknesses. The samples were thermally aged prior to the tests at a higher temperature (200°C) and in a shorter time (10–50 hours) than the previous experiments. The cross-sectional analyses of the Sn-2.5Ag joints without pre-aging consisting mostly of Cu6Sn5, showed a significant Cu dissolution while the Cu dissolution was not detected for the pre-aged joints with thick Cu3Sn layers. A large number of Kirkendall voids were also observed in the joints without pre-aging. The current stress tests on the controlled Cu3Sn joints showed that Cu3Sn layer thickness of more than 1.5 μm is effective in reducing Cu dissolution in the joints.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

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