Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

2002 ◽  
Author(s):  
H. Aoki ◽  
C. Takubo ◽  
T. Nakazawa ◽  
S. Honma ◽  
K. Doi ◽  
...  
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Assembly Process ◽  
Eutectic Solder ◽  
Chip Technology

Processing, Bumping and Assembly of Single Chip Plated Ni/Pd over ALCAP Bond Pads for Flip Chip Applications and Prototyping

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001841-001869
Author(s):  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
Paul N. Houston ◽  
Le hang La ◽  
Tim Spark
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Single Chip ◽  
Flip Chips ◽  
Chip Technology ◽  
Development Cycle ◽  
Before And After ◽  
Selective Plating ◽  
Bond Pads ◽  
Comprehensive Study

For Designer and Engineers, it is common during the process development cycle for new products to have limitations on the materials that are available for the prototype work. Most SMT devices are readily available in different formats/solder alloys to satisfy most of the needs for passive needs. However, many times IC devices are limited to what is available from the fab or an IC broker. These limitations can mean that die only come in aluminum, wirebond ready I/O metallization or that the silicon wafers already sawn and in single die formats. For applications where advancement in performance or miniaturization is needed, and the benefits of flip chip technology are attractive, then it is not trivial to be able to use these die. In these cases, the process of adding solderable plating technologies to the I/O bond pads is very favorable. The technologies are currently run for wafer lever plating baths, but very little has been done to evaluate single chip plating. Work in plating Ni/Pd onto the ALCAP structure has been performed to evaluate the process and feasibility of processing groups of singulated die with aluminum bond pads. The work to be detailed in this paper will go through the chemistries used in the plating process onto an aluminum bond pad that makes it suitable for flip chip processes. Several bumping structures, such as solder bumping over this plating technology and plating over gold or copper stud bumps, are evaluated. A process for bumping the flip chips is also detailed. The data for shear testing of the 10 variations before and after 500 liquid thermal shock cycles is detailed. Finally, a comprehensive study for assembly of solder bumped flip chips, with the selective plating process, will be detailed as well as a detailed analysis of the TC reliability of this assembly approach. It will be shown that selective Ni/Pd plating onto single, ALCAP bare die can allow for these typical wirebond die can be used in a practical approach solder flip chip process and provide reasonable reliability results when compared to a mainstream, wafer processed, solder bumped flip chip die.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

2018 ◽  
Vol 2018 (1) ◽  
pp. 000270-000276 ◽  
Author(s):  
Lei Fu ◽  
Milind Bhagavat ◽  
Ivor Barber
Keyword(s):  
Integrated Circuit ◽  
Seed Layer ◽  
High Performance ◽  
Flip Chip ◽  
Leading Edge ◽  
Lead Free ◽  
Assembly Process ◽  
Chip Technology ◽  
Layer Deposition ◽  
Ic Package

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

Predicting the Liquid Formation for the Solder Joints in Flip Chip Technology

2005 ◽  
Vol 128 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Wen-Hwa Chen ◽  
Shu-Ru Lin ◽  
Kuo-Ning Chiang
Keyword(s):  
Surface Tension ◽  
Solder Joint ◽  
Flip Chip ◽  
Solder Joints ◽  
Geometric Method ◽  
External Loading ◽  
Surface Evolver ◽  
Eutectic Solder ◽  
Chip Technology ◽  
Interfacial Surface

An accurate and efficient analytical geometric method is presented for predicting the geometric parameters of the controlled collapse chip connection type solder joint using direct chip attach technology after a reflow process. By this method, the meridian of the solder joint is first discretized as a series of sufficiently fine fragmental arcs. After calculating the internal pressure inside the molten eutectic solder from the forces balance, the meridional and circumferential radii of curvature of each arc are then obtained from the Laplace-Young equation. As a result, the coordinates of each node of the arc and the solder joint geometry can be determined in turn. The factors that affect the final shape of the molten eutectic solder joints, including the solder volumes, external loading, pad size, surface tension of molten eutectic solder, and interfacial surface tension between the molten eutectic solder and the solid high-lead bump are considered herein. The results computed by the analytical geometric method are also compared with those obtained using the Surface Evolver program, the extended Heinrich’s model, and the experimental results. The results of the various approaches are mutually consistent.

Applying system modeling to define 2.5 - d and 3 - d packaging roadmaps

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001983-002007
Author(s):  
Dev Gupta
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
System Modeling ◽  
New Technology ◽  
Smart Phone ◽  
Cost Effective ◽  
High Volume ◽  
Organic Substrate ◽  
Chip Technology ◽  
D Modules

Though work on 3-d and later 2.5-d packaging has been going on now for over 5 years, we do not yet see large applications in areas other than traditional heterogeneous integration e,g. in camera modules. Adoption of 2.5-d Si interposer technology in 2010-11 to build FPGA modules on a commercial scale had generated much enthusiasm and expectation that floodgates will open for wide use of this technology e,g. in every Smart Phone but that has not yet materialized, giving rise to a shift in attention in Blogs and Conferences from purely digital applications e,g. processor - memory modules to more performance driven and cost insensitive applications e,g. heterogeneous modules for electro - optic I/O in servers etc. Roadmaps for emerging technologies like 3-d stacking or 2.5-d modules are developed taking process maturity into consideration but they must also anticipate major applications. Such applications using a new technology can succeed only if there are overwhelming advantages in performance and system cost that negate increases in module costs. When the author and his team developed electroplated solder bump flip chip technology and their high volume implementation at two of the leading IDMs over 2 decades ago, both performance ( electrical ) and cost modeling were used to short list applications most likely to succeed and limit process development only for those applications. Countless users & providers of flip chip technology since then have benefited from this original work on electroplated solder and pillar bumps as well as build up type organic substrate technologies. A similar theoretical approach is sorely needed in the development of 2.5-d and 3-d technologies to define the most cost - effective configurations and focus development work on only those. In this work we will discuss the Bandwidth and Power consumption ( two of the key drivers for die stacking ) of various 2.5-d and 3-d package configurations and based on simulation results compare them. Key takeaways : 3-d stacking of dice using TSVs may not necessarily produce improved performance compared to less complicated packaging. Expensive interposers with high interconnect density may not even be necessary for most volume applications. Most likely configurations for processor - memory 3-d modules to get good enough bandwidth at lowest cost.

Reliable Low-Cost Flip Chip Interconnections

2001 ◽  
Author(s):  
Z. W. Zhong
Keyword(s):  
Mass Production ◽  
Flip Chip ◽  
Material Selection ◽  
Low Cost ◽  
Assembly Process ◽  
Eutectic Solder ◽  
Solder Bumps ◽  
Key Issues ◽  
Flip Chip Assembly ◽  
Reliability Performance

Abstract A few reliable low-cost flip chip assembly processes using gold bumps with NCA, ACF or ACP that involved daily mass production activities in the industry are reported in this paper. Some key issues of material selection and assembly for reliable low-cost flip chip interconnections are discussed. This paper also discusses reliable low-cost processes of flip chip on FR-4 using eutectic solder bumps with possible fewer process steps compared to the full assembly process. Some interesting results with respect to the reliability performance of the processes have been obtained.

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