Flip chip assembly process development, reliability assessment and process characterization for polymer stud grid array-chip scale package

2002 ◽  
Author(s):  
C.S. Paydenkar ◽  
F.G. Jefferson ◽  
D.F. Baldwin
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Reliability Assessment ◽  
Assembly Process ◽  
Process Characterization ◽  
Chip Scale Package ◽  
Flip Chip Assembly

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Corrections to "Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process"

2007 ◽  
Vol 30 (2) ◽  
pp. 359-359
Author(s):  
Robert W. Kay ◽  
Stoyan Stoyanov ◽  
Greg P. Glinski ◽  
Chris Bailey ◽  
Marc P. Y. Desmulliez
Keyword(s):  
Low Temperature ◽  
Flip Chip ◽  
Low Cost ◽  
Assembly Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Flip Chip Assembly

Influence of the Property of the Build-Up Package on Warpage at Flip Chip Assembly Process

2003 ◽  
Author(s):  
Yukihiko Toyoda ◽  
Yoichiro Kawamura ◽  
Hiroyoshi Hiei ◽  
Qiang Yu ◽  
Tadahiro Shibutani ◽  
...  
Keyword(s):  
Flip Chip ◽  
Electronic Device ◽  
New Product ◽  
High Density ◽  
Simulation Technique ◽  
Assembly Process ◽  
Reliability Problem ◽  
Fine Pitch ◽  
Flip Chip Assembly ◽  
Single Material

High density and integrated packaging of electronic device requires fine pitch. This packaging causes reliability problem in electronic device. One of them, warpage of the package occurred at chip assembly process may affect reliability. Therefore, if the simulation at the time of a chip assembly process is possible, it will be able to evaluate warpage in advance. It is very effective for development of a new product. Then, in this paper, the build-up package is regarded as a single material and the simulation technique of accuracy warpage at the time of chip assembly is reported. Next it is investigated the simulation technique for package warpage at the chip assembly process. Finnaly, it analyzed about the properties which affect warpage.

Impact of Mechanical Simulation Methodology on Electronic Package Reliability Assessment with Applications to 3D TSS Technology

2010 ◽  
Vol 2010 (1) ◽  
pp. 000170-000175
Author(s):  
Zhongping Bao ◽  
James Burrell
Keyword(s):  
Product Development ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Reliability Assessment ◽  
Assembly Process ◽  
Development Cost ◽  
Mechanical Reliability ◽  
Simulation Methodology ◽  
Mechanical Simulation ◽  
Package Reliability

Mechanical reliability issues in electronic packages have drawn significant attention in semiconductor industry for decades and have increased product development cost significantly. Recent rapid growth of various portable electronic devices like smartphone and smartbook with increasing demand for more functionality in tighter space further challenges the limit of mechanical reliability. To reduce the product development cost and time-to-market, mechanical simulation has been extensively employed in semiconductor industry for the purpose of design optimization and reliability assessment. The importance of having the correct simulation methodology can't be overemphasized considering the extent of its utilization throughout the product development cycle. In this paper, we will discuss three fundamental mechanical modeling methodologies that are widely used for simulating flip-chip overmolded packages. These approaches are generally used to simulate package warpage at End-of-Line (EOL) as well as to assess package reliability from a stress point of view. The first approach we studied in this paper is to assume that the package is initially stress-free at a given uniform temperature, which is usually taken to be the peak temperature of the mold cure profile. However, this differs from the actual assembly process where package composition and cure profiles are different at each assembly processing step. The second approach simply accounts for that fact and assigns different stress-free temperature to each individual package component. For example, the die is assumed to be stress-free at the chip attach temperature and substrate is assumed to be stress-free instead at the substrate baking temperature. This approach captures more physics compared to the first approach. The last approach explores that idea further by simulating the actual assembly process, step by step, through element removal and addition techniques available in the software. Such study is also carried out for a flip-chip overmolded package with Through-Silicon-Stacking (TSS) technology. Both Die-to-Die-first (D2D) and Die-to-Substrate-first (D2S) processes are examined. Simulated warpage, as well as reliability assessment regarding different failure mechanisms using these three modeling methodologies are discussed in detail. The paper is prepared to the best knowledge of authors and those statements do not necessarily reflect opinions of Qualcomm Inc. Some data shared in this paper is normalized such that no commercial confidential information is published.

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