A 20–44 GHz Wideband LNA Design Using the SiGe Technology for 5G Millimeter-Wave Applications

This paper presents the design and implementation of a low-noise amplifier (LNA) for millimeter-wave (mm-Wave) 5G wireless applications. The LNA was based on a common-emitter configuration with cascode amplifier topology using an IHP’s 0.13 μm Silicon Germanium (SiGe) heterojunction bipolar transistor (HBT) whose f_T/f_MAX/gate-delay is 360/450 GHz/2.0 ps, utilizing transmission lines for simultaneous noise and input matching. A noise figure of 3.02–3.4 dB was obtained for the entire wide bandwidth from 20 to 44 GHz. The designed LNA exhibited a gain (S_21) greater than 20 dB across the 20–44 GHz frequency range and dissipated 9.6 mW power from a 1.2 V supply. The input reflection coefficient (S_11) and output reflection coefficient (S_22) were below −10 dB, and reverse isolation (S_12) was below −55 dB for the 20–44 GHz frequency band. The input 1 dB (P1dB) compression point of −18 dBm at 34.5 GHz was obtained. The proposed LNA occupies only a 0.715 mm2 area, with input and output RF (Radio Frequency) bond pads. To the authors’ knowledge, this work evidences the lowest noise figure, lowest power consumption with reasonable highest gain, and highest bandwidth attained so far at this frequency band in any silicon-based technology.

Solderability and Reliability of Sintered Nano-Ag Bond Pads of Printed Re-Distribution Layer (RDL)

Re-distribution layer (RDL) is one key enabling technology for advance packaging. RDL is usually fabricated in wafer level by photolithography process. An alternative approach for implementing RDL by additive manufacturing (AM) method is proposed in this study. This allows RDL to be fabricated on singulation chip. Nano-silver (nano-Ag) ink is printed on the silicon chip to form routing traces and bond pads. However, the Ag pad may be consumed by solder quickly if the process is not properly controlled. This paper studied the effect of nano-Ag ink sintering condition on the solderability of Ag pad. The solder joint mechanical integrity was evaluated by solder ball shear test. High temperature storage test was also carried out to evaluate the solder joint reliability. Experiment results showed that Ag pad fabricated by AM is SMT compatible. High temperature storage did not cause early failure to the samples. There was not significant change in the Ag3Sn IMC layer thickness and mechanical strength. The finding of the present study will serve as a very useful reference for future practice of forming solder joints on sintered nano-Ag pads.

Enhanced Ball Shear Testing Configuration For Substrate LGA Sensor Devices

Semiconductor assembly mass production environment has means of testing and verifying bond consistency and reliability during wire bonding. Common bond integrity assessment is ball shear testing (BST). This test enables analysis of the strength between the bond pad and a ball bond. This paper presents significant procedure on how ball shear testing parameters should be treated during wirebond integrity check. Device complexity in terms of performing ball shear testing specifically on sensor dice has different output responses. Frequent shearing on die resulted as bond pads are elevated by 30 µm (microns). To address manufacturing in-process controls challenges, shearing tool position, dage settings, and optical scopes are taken into consideration. Also, a study was performed on the execution correctness in combination with proper dage parameters was explored to meet good ball shear test process capability and break modes.

Resolution of Low IMC on Multi-Stacked Dice Device with Different Bond Pads

The continuing advances of die technology of integrated circuits (IC) miniaturization bringing more complexity in the product. At unusual conditions one may encounter new challenges intrinsic to the structure of the package. The study aims to qualify a product such as multi-stacked dice configurations with baseline reference using same die technology. The only difference is the substrate layout in which defined for the electrical purpose. The challenge is to understand and resolve low intermetallic coverage (IMC) on each die which may lead to manufacturability and reliability problems over time.

Failure Analysis of Wire Bonding on Strain Gauge Contact Pads Using FIB, SEM, and Elemental Mapping

Stacks consisting of titanium, platinum, and gold layers constitute a popular metallization system for the bond pads of semiconductor chips. Wire bonding on such layer stacks at different temperatures has extensively been investigated in the past. However, reliable information on the bondability of this metallization system after a high-temperature sintering process is still missing. When performing wire bonding after pressure sintering (at, e.g., 875 °C), bonding failures may occur that must be identified and analyzed. In the present study, a focused ion beam (FIB), scanning electron microscopy (SEM), and elemental mapping are utilized to characterize the root cause of failure. As a probable root cause, the infusion of metallization layers is found which causes an agglomerate formation at the interface of approximately 2 μm height difference on strain gauge contact pads and possibly an inhomogeneous mixing of layers as a consequence of the high-temperature sintering process. Potential treatment to tackle this agglomeration with the removal of the above-mentioned height difference during the process of contact pad structuring and alternative electrical interconnect methodologies are hereby suggested in this paper.

Cl-Containing Microplastics from the Environment

One of the critical process steps in the assembly of integrated circuits is the making of the connection between the silicon chip and the outside world. This is done by a thermo-sonic welding process of sometimes more than 800 copper wires to the aluminum bond pads. The Al-Cu intermetallic compound formed during this process is sensitive for trace amount of chloride from the environment. It is found that Cl-containing microplastics are the source of this chloride and further analyzing these particles helps to identify the origin of these particles.

Parameter Optimization for Unstable Pin Bonding

Plastic frame power modules with press-fitted or molded pins create challenging bonding conditions. Pin stability variations, from relatively stable to unstable within a single power module, makes it difficult to find process parameters that fit to all pins equally well. Also, tight space, full utilization of the pin surface for bonding and a large number of pins per module makes clamping solutions difficult or impractical. Therefore, we used process optimization to find optimal process parameters for the unstable pin bonds and active process control feature to reduce deformation variance in bonding. The study revealed the importance of the cleaning phase optimization for both sides of the pin stability variations. We found that ensuring a good cleaning phase, typically within first 10ms of the process on the unstable pins, significantly improved the quality of the bonds. Unstable pins tended to lift after bonding with traditional parameters, but demonstrated good shear strength with optimized parameters. Active process control ensured that all bonds reached optimal deformation, regardless of the pin stability. Generally, the best approach to reach good bond quality is to ensure an optimal bonding environment, including clean and stable bond pads. However, when it is not possible or practical to stabilize the bond pad, this study shows that carefully executed process optimization combined with the active process control can lead to robust bonding on unstable pins.

(ECS Meeting PRiME 2020) High TEC copper to connect copper bond pads for low temperature wafer bonding

Copper to copper wafer hybrid bonding is the most promising technology for three-dimensional (3D) integration. In the hybrid bonding process, two silicon wafers are aligned and contacted. At room temperature, these aligned copper pads contain radial-shaped nanometer-sized hollows due to the dishing effect induced by chemical-mechanical polishing (CMP). These wafers are annealed for copper to expand and connect upper and lower pads. This copper expansion is key to eliminate the radial-shaped hollows and make copper pads contacted. Therefore, in this research, we investigated the new high thermal expansion coefficient (TEC) electrodeposited copper to eliminate dishing hollows at lower temperature than that with conventional copper using the combination of new additive A and three other additives. The TEC of new electrodeposited copper is 25.2 x 10-6 oC-1, 46% higher than conventional copper and the calculated contact area of copper surface at 250oC with 5 nm dishing depth is 100%.

Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier–tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.