No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

Pre-Applied Underfill (PAUF) for Fine Pitch Flip Chip 3D Chip Stacking

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001432-001451
Author(s):  
Anupam Choubey ◽  
E. Anzures ◽  
A. Dhoble ◽  
D. Fleming ◽  
M. Gallagher ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Fatigue Testing ◽  
Electrical Performance ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
Semiconductor Packages ◽  
Reliability Performance ◽  
3D Chip Stacking

Current demands of the industry on performance and cost has triggered the electronics industry to use high I/O counts semiconductor packages. Copper pillar technology has been widely adopted for introducing high I/O counts in Flip Chip and 3D Chip Stacking. With the introduction of flipchip technology new avenues have been generated involving 3D chip stacking to expand the need for high performance. With the increase in the demand for high density, copper pillar technology is being adopted in the industry to address the fine pitch requirements in addition to providing enhanced thermal and electrical performance. For this study, Copper pillars and SnAg were electrolytically deposited using Dow's electroplating chemistry on internally developed test structures. After plating, wafers were diced and bonded using thermocompression bonding techniques. Copper pillar technology has been enabled to pass reliability requirements by using Underfill materials during the bonding. Underfill materials assist in redistributing the stress generated during reliability such as thermal fatigue testing. Out of the several Underfill technologies available, we have focused on pre-applied or wafer level underfill materials with 60% silica filler for this study. In the pre-applied underfill process the underfill is applied prior to bonding by coating directly on the whole wafer. Pre-applied underfill reduces the underfill dispense process time by being present prior to bonding. In this study, we have demonstrated the application of wafer level underfill for fine pitch bonding of internally developed test vehicles with SnAg-capped copper pillars with 25 μm diameter and 50 μm bump pitch. This paper demonstrates bonding alignment for fine pitch assembly with wafer level underfill to achieve 100% good solder joins after bonding. Wafer level underfill has been demonstrated successfully to bond and pass JEDEC level 3 preconditioning and standard TCT, HTS and HAST reliability tests. This paper also discusses defect mechanisms which have been found to optimize the bonding process and reliability performance. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

2015 ◽  
Vol 2015 (1) ◽  
pp. 000822-000826 ◽  
Author(s):  
Won Kyoung Choi ◽  
Duk Ju Na ◽  
Kyaw Oo Aung ◽  
Andy Yong ◽  
Jaesik Lee ◽  
...  
Keyword(s):  
High Performance ◽  
Process Development ◽  
Cost Effective ◽  
Access Point ◽  
Data Access ◽  
Memory Device ◽  
Logic Device ◽  
Wafer Level ◽  
Component Level ◽  
Fine Pitch

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2μm line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000809-000825
Author(s):  
Bernard Adams ◽  
Won Kyung Choi ◽  
Duk Ju Na ◽  
Andy Yong ◽  
Seung Wook Yoon ◽  
...  
Keyword(s):  
Line Width ◽  
High Performance ◽  
Process Development ◽  
Data Access ◽  
Electrical Performance ◽  
Logic Device ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Fine Pitch

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill

2010 ◽  
Vol 2010 (1) ◽  
pp. 000798-000805 ◽  
Author(s):  
Sangil Lee ◽  
Daniel F. Baldwin
Keyword(s):  
Flip Chip ◽  
Void Nucleation ◽  
Void Formation ◽  
Bubble Nucleation ◽  
Nucleation Theory ◽  
High Yield ◽  
Process Conditions ◽  
Assembly Process ◽  
Fine Pitch ◽  
Underfill Material

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield. In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7% ) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively. This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results.

Corrections to "Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process"

2007 ◽  
Vol 30 (2) ◽  
pp. 359-359
Author(s):  
Robert W. Kay ◽  
Stoyan Stoyanov ◽  
Greg P. Glinski ◽  
Chris Bailey ◽  
Marc P. Y. Desmulliez
Keyword(s):  
Low Temperature ◽  
Flip Chip ◽  
Low Cost ◽  
Assembly Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Flip Chip Assembly

Microbump Processing for 3D IC Integration

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001028-001049
Author(s):  
Feng Li ◽  
Andrew W. Owens ◽  
Qianyi Li
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Bonding Process ◽  
Replication Process ◽  
Spatial Efficiency ◽  
Bonding Structure ◽  
Fine Pitch ◽  
Bonding Method ◽  
Self Replication

In recent years, the development of microbumps has allowed even smaller sizes of ICs to utilize the flip chip technique. In addition, microbumps have enabled the implementation of three-dimensional (3D) ICs, which drastically improve the spatial efficiency of packaging. However, as the bumps size decreases and the number increases, several process challenges must be considered, for example, the height consistency of bump, the ratio of miss and deformity bump and the yield and strength of interconnection, etc. Therefore, it is increasingly important to study the interconnection technology and materials of high-density microbump interconnection. After briefly introducing the common electronic packaging techniques, including wire bonding, tape-automated bonding and flip chip, this paper reviews microbumps as an advanced bonding technology. Techniques such as Controlled Collapse Chip Connection - New Process(C4NP), printing, insert bump bonding, and self-replication process are discussed and compared. C4NP can achieve low-cost, fine pitch bumping by utilizing varied lead-free solder alloys, which overcomes the limitation of existing bumping technologies. Depending on the microbump size, engraved mask stump, and photosensitive organic mask and squeegee are the two ways for micro-bump printing. The micro-insert bump bonding process is new to stack chips vertically, which has robust bonding structure and a simpler bonding process compared to Cu pillar bonding process. The self-replication process is using the surface tension property of molten solder between the micro bridged bump to get two bumps with same volume and geometries on each faced pairs of lands. The use of two common material for the microbump, Cu, Sn, and its alloys are presented along with the differences in the process for each. As with any technology, a new breakthrough addressing an issue brings with it its own set of shortfalls. Microbumps are no different. The various techniques and materials used to realize the reduced scale bonding method are subject to a number of challenges. Most prominent among them are electromigration, thermomigration, and thermallyinduced mechanical fatigue, which are discussed in this paper.

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