Case Studies on Transition Fault Test Generation for At-speed Scan Testing

Author(s):  
Nor Azura Zakaria ◽  
Edward V. Bautista Jr. ◽  
Suhaimi Bahisham Jusoh ◽  
Weng Fook Lee ◽  
Xiaoqing Wen
2010 ◽  
Vol 83 (12) ◽  
pp. 2369-2378 ◽  
Author(s):  
Daniel Hoffman ◽  
Hong-Yi Wang ◽  
Mitch Chang ◽  
David Ly-Gagnon ◽  
Lewis Sobotkiewicz ◽  
...  
Keyword(s):  

Author(s):  
X. Wen ◽  
K. Enokimoto ◽  
K. Miyase ◽  
Y. Yamato ◽  
M. A. Kochte ◽  
...  
Keyword(s):  

Author(s):  
X. Wen ◽  
K. Miyase ◽  
S. Kajihara ◽  
H. Furukawa ◽  
Y. Yamato ◽  
...  
Keyword(s):  

2019 ◽  
Vol 18 (1) ◽  
pp. 231-236
Author(s):  
Yuta Yamato ◽  
Xiaoqing Wen ◽  
Kohei Miyase ◽  
Hiroshi Furukawa ◽  
Seiji Kajihara

Author(s):  
Xiaoqing Wen ◽  
Y. Yamashita ◽  
S. Kajihara ◽  
Laung-Terng Wang ◽  
K.K. Saluja ◽  
...  

2021 ◽  
Vol 26 (4) ◽  
pp. 1-15
Author(s):  
Irith Pomeranz

A recent work showed that it is possible to transform a single-cycle test for stuck-at faults into a launch-on-shift (LOS) test that is guaranteed to detect the same stuck-at faults without any logic or fault simulation. The LOS test also detects transition faults. This was used for obtaining a compact LOS test set that detects both types of faults. In the scenario where LOS tests are used for both stuck-at and transition faults, this article observes that, under certain conditions, the detection of a stuck-at fault guarantees the detection of a corresponding transition fault. This implies that the two faults are equivalent under LOS tests. Equivalence can be used for reducing the set of target faults for test generation and test compaction. The article develops this notion of equivalence under LOS tests with equal primary input vectors and provides an efficient procedure for identifying it. It presents experimental results to demonstrate that such equivalences exist in benchmark circuits, and shows an unexpected effect on a test compaction procedure.


2017 ◽  
Vol 6 (1) ◽  
pp. 36-46
Author(s):  
Hemanth Kumar Motamarri ◽  
B. Leela Kumari

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.


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