A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

2008 ◽  
Author(s):  
X. Wen ◽  
K. Miyase ◽  
S. Kajihara ◽  
H. Furukawa ◽  
Y. Yamato ◽  
...  
Keyword(s):  
Test Generation ◽  
Scan Testing

Power-aware test generation with guaranteed launch safety for at-speed scan testing

2011 ◽  
Author(s):  
X. Wen ◽  
K. Enokimoto ◽  
K. Miyase ◽  
Y. Yamato ◽  
M. A. Kochte ◽  
...  
Keyword(s):  
Test Generation ◽  
Scan Testing

Power-aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing

2019 ◽  
Vol 18 (1) ◽  
pp. 231-236
Author(s):  
Yuta Yamato ◽  
Xiaoqing Wen ◽  
Kohei Miyase ◽  
Hiroshi Furukawa ◽  
Seiji Kajihara
Keyword(s):  
Test Generation ◽  
Yield Loss ◽  
Scan Testing

On low-capture-power test generation for scan testing

2005 ◽  
Author(s):  
Xiaoqing Wen ◽  
Y. Yamashita ◽  
S. Kajihara ◽  
Laung-Terng Wang ◽  
K.K. Saluja ◽  
...  
Keyword(s):  
Test Generation ◽  
Scan Testing ◽  
Power Test

Case Studies on Transition Fault Test Generation for At-speed Scan Testing

2010 ◽  
Author(s):  
Nor Azura Zakaria ◽  
Edward V. Bautista Jr. ◽  
Suhaimi Bahisham Jusoh ◽  
Weng Fook Lee ◽  
Xiaoqing Wen
Keyword(s):  
Case Studies ◽  
Test Generation ◽  
Scan Testing ◽  
Transition Fault

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

2008 ◽  
Vol 24 (4) ◽  
pp. 379-391 ◽  
Author(s):  
Xiaoqing Wen ◽  
Kohei Miyase ◽  
Tatsuya Suzuki ◽  
Seiji Kajihara ◽  
Laung-Terng Wang ◽  
...  
Keyword(s):  
Test Generation ◽  
Switching Activity ◽  
Scan Testing ◽  
Ir Drop ◽  
Activity Test

Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation

2003 ◽  
Author(s):  
Michael B. Schmidt ◽  
Noor Jehan Saujauddin
Keyword(s):  
Failure Analysis ◽  
Large Scale ◽  
Fault Isolation ◽  
Electronic Information ◽  
Scan Testing ◽  
Challenging Environment ◽  
Contrast Technique ◽  
Defect Isolation ◽  
Voltage Contrast ◽  
Higher Sensitivity

Abstract Scan testing and passive voltage contrast (PVC) techniques have been widely used as failure analysis fault isolation tools. Scan diagnosis can narrow a failure to a given net and passive voltage contrast can give real-time, large-scale electronic information about a sample at various stages of deprocessing. In the highly competitive and challenging environment of today, failure analysis cycle time is very important. By combining scan FA with a much higher sensitivity passive voltage contrast technique, one can quickly find defects that have traditionally posed a great challenge.

Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

2011 ◽  
Author(s):  
Yu Huang ◽  
Wu-Tung Cheng ◽  
Ting-Pu Tai ◽  
Liyang Lai ◽  
Ruifeng Guo ◽  
...  
Keyword(s):  
Hold Time ◽  
Clock Signal ◽  
Clock Tree ◽  
Scan Testing ◽  
Design Error ◽  
Functional Logic ◽  
Scan Chains ◽  
Delay Defects

Abstract If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

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