On Using Test Vector Differences for Reducing Test Pin Numbers

2005 ◽  
Author(s):  
M.-L. Flottes ◽  
R. Poirier ◽  
B. Rouzeyre
Keyword(s):  
Test Vector

scholarly journals Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2505
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Fault Coverage ◽  
Test Vector ◽  
Single Event Upset ◽  
Fault Models ◽  
Test Program ◽  
Global Test ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction ◽  
Selection Of

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

BIST technique by equally spaced test vector sequences

2004 ◽  
Author(s):  
S. Manich ◽  
L. Garcia ◽  
L. Balado ◽  
E. Lupon ◽  
J. Rius ◽  
...  
Keyword(s):  
Test Vector ◽  
Vector Sequences
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