Deterministic Test Vector Compression / Decompression Using an Embedded Processor

Dependable Computing - EDCC 5 - Lecture Notes in Computer Science ◽

10.1007/11408901_24 ◽

2005 ◽

pp. 318-331

Author(s):

Maciej Bellos ◽

Dimitris Nikolos

Keyword(s):

Test Vector ◽

Embedded Processor ◽

Test Vector Compression

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Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation - Frontiers in Electronic Testing ◽

10.1007/978-1-4757-6527-4_9 ◽

2002 ◽

pp. 139-150 ◽

Cited By ~ 5

Author(s):

Abhijit Jas ◽

Nur A. Touba ◽

Krishnendu Chakrabarty

Keyword(s):

Test Vector ◽

Embedded Processor ◽

Test Vector Compression

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An efficient test vector compression technique based on geometric shapes [system-on-a-chip]

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) ◽

10.1109/icecs.2001.957514 ◽

2002 ◽

Cited By ~ 2

Author(s):

S. al Zahir ◽

A. El-Maleh ◽

E. Khan

Keyword(s):

Test Vector ◽

Compression Technique ◽

Geometric Shapes ◽

Efficient Test ◽

System On A Chip ◽

Test Vector Compression

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Efficient algorithm for test vector decompression using an embedded processor

2014 IEEE AUTOTEST ◽

10.1109/autest.2014.6935172 ◽

2014 ◽

Cited By ~ 1

Author(s):

Kamran Saleem ◽

Nur A. Touba

Keyword(s):

Efficient Algorithm ◽

Test Vector ◽

Embedded Processor

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A Software-Based Method for Test Vector Compression in Testing System-on-a-Chip

2006 IEEE Instrumentation and Measurement Technology Conference Proceedings ◽

10.1109/imtc.2006.236789 ◽

2006 ◽

Author(s):

Satyendra Biswas

Keyword(s):

Testing System ◽

Test Vector ◽

System On A Chip ◽

Test Vector Compression

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Survey of Test Vector Compression Techniques

IEEE Design & Test of Computers ◽

10.1109/mdt.2006.105 ◽

2006 ◽

Vol 23 (4) ◽

pp. 294-303 ◽

Cited By ~ 308

Author(s):

N.A. Touba

Keyword(s):

Test Vector ◽

Test Vector Compression

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An efficient test vector compression scheme using selective huffman coding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2003.811452 ◽

2003 ◽

Vol 22 (6) ◽

pp. 797-806 ◽

Cited By ~ 191

Author(s):

A. Jas ◽

J. Ghosh-Dastidar ◽

Mom-Eng Ng ◽

N.A. Touba

Keyword(s):

Huffman Coding ◽

Test Vector ◽

Compression Scheme ◽

Efficient Test ◽

Test Vector Compression

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Test vector compression using EDA-ATE synergies

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) ◽

10.1109/vts.2002.1011118 ◽

2003 ◽

Cited By ~ 32

Author(s):

A. Khoche ◽

E. Volkerink ◽

J. Rivoir ◽

S. Mitra

Keyword(s):

Test Vector ◽

Test Vector Compression

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Test vector compression technique in system-on-chip

2009 IEEE Intrumentation and Measurement Technology Conference ◽

10.1109/imtc.2009.5168623 ◽

2009 ◽

Author(s):

Satyendra N. Biswas ◽

Sunil R. Das ◽

Mansour H. Assaf ◽

Altaf Hossain

Keyword(s):

System On Chip ◽

Test Vector ◽

Compression Technique ◽

On Chip ◽

Test Vector Compression

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Test vector compression via statistical coding and dynamic compaction

2000 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology Conference. Future Sustainment for Military Aerospace (Cat. No.00CH37057) ◽

10.1109/autest.2000.885613 ◽

2002 ◽

Author(s):

Mom Eng Ng ◽

N.A. Touba

Keyword(s):

Dynamic Compaction ◽

Test Vector ◽

Statistical Coding ◽

Test Vector Compression

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On System-on-Chip Testing Using Hybrid Test Vector Compression

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2014.2313431 ◽

2014 ◽

Vol 63 (11) ◽

pp. 2611-2619 ◽

Cited By ~ 4

Author(s):

Satyendra N. Biswas ◽

Sunil R. Das ◽

Emil M. Petriu

Keyword(s):

System On Chip ◽

Test Vector ◽

Hybrid Test ◽

Chip Testing ◽

On Chip ◽

Test Vector Compression

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