Proceedings International Test Conference 2001 (Cat. No.01CH37260)
Latest Publications

TOTAL DOCUMENTS

130

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Published By IEEE

0780371690

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Test vector encoding using partial LFSR reseeding

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966711 ◽

2002 ◽

Cited By ~ 150

Author(s):

C.V. Krishna ◽

A. Jas ◽

N.A. Touba

Keyword(s):

Test Vector ◽

Lfsr Reseeding

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A study of bridging defect probabilities on a Pentium (TM) 4 CPU

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966689 ◽

2002 ◽

Cited By ~ 51

Author(s):

V. Krishnaswamy ◽

A.B. Ma ◽

P. Vishakantaiah

Keyword(s):

Bridging Defect

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Test path simulation and characterisation

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966658 ◽

2002 ◽

Cited By ~ 7

Author(s):

K. Helmreich

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Two-dimensional test data compression for scan-based deterministic BIST

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966712 ◽

2002 ◽

Cited By ~ 50

Author(s):

Hua-Guo Liang ◽

S. Hellebrand ◽

H.-J. Wunderlich

Keyword(s):

Data Compression ◽

Test Data ◽

Two Dimensional ◽

Test Data Compression ◽

Deterministic Bist

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On efficient error diagnosis of digital circuits

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966688 ◽

2002 ◽

Cited By ~ 10

Author(s):

N. Sridhar ◽

M.S. Hsiao

Keyword(s):

Digital Circuits ◽

Error Diagnosis

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Optimal production test times through adaptive test programming

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966714 ◽

2002 ◽

Cited By ~ 31

Author(s):

S. Benner ◽

O. Boroffice

Keyword(s):

Production Test ◽

Optimal Production ◽

Adaptive Test ◽

Test Programming

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Low hardware overhead scan based 3-weight weighted random BIST

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966709 ◽

2002 ◽

Cited By ~ 36

Author(s):

Seongrnoon Wang

Keyword(s):

Hardware Overhead

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Test and repair of large embedded DRAMs. I

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966630 ◽

2002 ◽

Cited By ~ 8

Author(s):

R. McConnell ◽

R. Rajsuman

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Scan array solution for testing power and testing time

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966685 ◽

2002 ◽

Cited By ~ 3

Author(s):

Lei Xu ◽

Yihe Sun ◽

Hongyi Chen

Keyword(s):

Testing Time ◽

Testing Power

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At-speed logic BIST using a frozen clock testing strategy

Proceedings International Test Conference 2001 (Cat. No.01CH37260) ◽

10.1109/test.2001.966619 ◽

2002 ◽

Cited By ~ 1

Author(s):

Jongshin Shin ◽

Xiaoming Yu ◽

E.M. Rudnick ◽

M. Abramovici

Keyword(s):

Testing Strategy ◽

Logic Bist

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Proceedings International Test Conference 2001 (Cat. No.01CH37260)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Test vector encoding using partial LFSR reseeding

A study of bridging defect probabilities on a Pentium (TM) 4 CPU

Test path simulation and characterisation

Two-dimensional test data compression for scan-based deterministic BIST

On efficient error diagnosis of digital circuits

Optimal production test times through adaptive test programming

Low hardware overhead scan based 3-weight weighted random BIST

Test and repair of large embedded DRAMs. I

Scan array solution for testing power and testing time

At-speed logic BIST using a frozen clock testing strategy

Proceedings International Test Conference 2001 (Cat. No.01CH37260)
Latest Publications