test vector compression Latest Research Papers

Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits

Indian Journal of Science and Technology ◽

10.17485/ijst/2016/v9i30/85750 ◽

2016 ◽

Vol 9 (30) ◽

Cited By ~ 2

Author(s):

Anju Asokan ◽

J. P. Anita

Keyword(s):

Digital Circuits ◽

Test Vector ◽

Burrows Wheeler Transform ◽

Test Vector Compression

Download Full-text

On System-on-Chip Testing Using Hybrid Test Vector Compression

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2014.2313431 ◽

2014 ◽

Vol 63 (11) ◽

pp. 2611-2619 ◽

Cited By ~ 4

Author(s):

Satyendra N. Biswas ◽

Sunil R. Das ◽

Emil M. Petriu

Keyword(s):

System On Chip ◽

Test Vector ◽

Hybrid Test ◽

Chip Testing ◽

On Chip ◽

Test Vector Compression

Download Full-text

Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2014.2314307 ◽

2014 ◽

Vol 33 (8) ◽

pp. 1219-1230 ◽

Cited By ~ 2

Author(s):

Joon-Sung Yang ◽

Jinkyu Lee ◽

Nur A. Touba

Keyword(s):

Test Vector ◽

Test Vector Compression

Download Full-text

A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding

2009 15th IEEE Pacific Rim International Symposium on Dependable Computing ◽

10.1109/prdc.2009.11 ◽

2009 ◽

Author(s):

Huag Liang ◽

Wenfa Zhan ◽

Qiang Luo ◽

Cuiyun Jiang

Keyword(s):

Test Vector ◽

Logic Operation ◽

Test Vector Compression

Download Full-text

Test vector compression technique in system-on-chip

2009 IEEE Intrumentation and Measurement Technology Conference ◽

10.1109/imtc.2009.5168623 ◽

2009 ◽

Author(s):

Satyendra N. Biswas ◽

Sunil R. Das ◽

Mansour H. Assaf ◽

Altaf Hossain

Keyword(s):

System On Chip ◽

Test Vector ◽

Compression Technique ◽

On Chip ◽

Test Vector Compression

Download Full-text

A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC)

2009 13th International Conference on Computer Supported Cooperative Work in Design ◽

10.1109/cscwd.2009.4968028 ◽

2009 ◽

Cited By ~ 1

Author(s):

Wenfa Zhan ◽

Aiman El-Maleh

Keyword(s):

Test Vector ◽

Run Length ◽

Run Length Coding ◽

Test Vector Compression

Download Full-text

VLSI Circuit Test Vector Compression Technique

2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007 ◽

10.1109/imtc.2007.379055 ◽

2007 ◽

Cited By ~ 3

Author(s):

Satyendra Biswas ◽

Sunil R. Das ◽

Altaf Hossain

Keyword(s):

Vlsi Circuit ◽

Test Vector ◽

Compression Technique ◽

Test Vector Compression

Download Full-text

A Software-Based Method for Test Vector Compression in Testing System-on-a-Chip

2006 IEEE Instrumentation and Measurement Technology Conference Proceedings ◽

10.1109/imtc.2006.236789 ◽

2006 ◽

Author(s):

Satyendra Biswas

Keyword(s):

Testing System ◽

Test Vector ◽

System On A Chip ◽

Test Vector Compression

Download Full-text

An Efficient Test Vector Compression Technique Based on Block Merging

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1692868 ◽

2006 ◽

Author(s):

A. El-Maleh

Keyword(s):

Test Vector ◽

Compression Technique ◽

Efficient Test ◽

Test Vector Compression

Download Full-text

Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding

24th IEEE VLSI Test Symposium ◽

10.1109/vts.2006.25 ◽

2006 ◽

Cited By ~ 4

Author(s):

J. Lee ◽

N.A. Touba

Keyword(s):

Test Vector ◽

Non Linear ◽

Test Vector Compression

Download Full-text

test vector compression
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits

On System-on-Chip Testing Using Hybrid Test Vector Compression

Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression

A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding

Test vector compression technique in system-on-chip

A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC)

VLSI Circuit Test Vector Compression Technique

A Software-Based Method for Test Vector Compression in Testing System-on-a-Chip

An Efficient Test Vector Compression Technique Based on Block Merging

Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding

Export Citation Format

test vector compressionRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Burrows Wheeler Transform Based Test Vector Compression for Digital Circuits

On System-on-Chip Testing Using Hybrid Test Vector Compression

Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression

A Test Vector Compression/Decompression Scheme Based on Logic Operation between Adjacent Bits (LOBAB) Coding

Test vector compression technique in system-on-chip

A new collaborative scheme of test vector compression based on equal-run-length coding (ERLC)

VLSI Circuit Test Vector Compression Technique

A Software-Based Method for Test Vector Compression in Testing System-on-a-Chip

An Efficient Test Vector Compression Technique Based on Block Merging

Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding

test vector compression
Recently Published Documents