Test Compaction for Transition Faults under Transparent-Scan

2006 ◽  
Author(s):  
I. Pomeranz ◽  
S.M. Reddy
Keyword(s):  
Test Compaction ◽  
Transition Faults

Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors

2021 ◽  
Vol 26 (4) ◽  
pp. 1-15
Author(s):  
Irith Pomeranz
Keyword(s):  
Test Generation ◽  
Fault Simulation ◽  
Single Cycle ◽  
Primary Input ◽  
Test Set ◽  
Efficient Procedure ◽  
Test Compaction ◽  
Transition Faults ◽  
Transition Fault ◽  
Types Of Faults

A recent work showed that it is possible to transform a single-cycle test for stuck-at faults into a launch-on-shift (LOS) test that is guaranteed to detect the same stuck-at faults without any logic or fault simulation. The LOS test also detects transition faults. This was used for obtaining a compact LOS test set that detects both types of faults. In the scenario where LOS tests are used for both stuck-at and transition faults, this article observes that, under certain conditions, the detection of a stuck-at fault guarantees the detection of a corresponding transition fault. This implies that the two faults are equivalent under LOS tests. Equivalence can be used for reducing the set of target faults for test generation and test compaction. The article develops this notion of equivalence under LOS tests with equal primary input vectors and provides an efficient procedure for identifying it. It presents experimental results to demonstrate that such equivalences exist in benchmark circuits, and shows an unexpected effect on a test compaction procedure.

A New Technique for Scan Chain Failure Diagnosis

2002 ◽  
Author(s):  
Ruifeng Guo ◽  
Srikanth Venkataraman
Keyword(s):  
Hold Time ◽  
Failure Diagnosis ◽  
Second Step ◽  
Fault Type ◽  
Transition Faults ◽  
Input Side ◽  
Output Side ◽  
A New Technique ◽  
Scan Chain ◽  
Diagnostic Resolution

Abstract In this paper, we present a scan chain fault diagnosis procedure. The diagnosis for a single scan chain failure is performed in three steps. The first step uses special chain test patterns to determine both the faulty chain and the fault type in the faulty chain. The second step uses a novel procedure to generate special test patterns to identify the suspect scan cell within a range of scan cells. Unlike previously proposed methods that restrict the location of the faulty scan cell only from the scan chain output side, our method restricts the location of the faulty scan cell from both the scan chain output side and the scan chain input side. Hence the number of suspect scan cells is reduced significantly in this step. The final step further improves the diagnostic resolution by ranking the suspect scan cells inside this range. The proposed technique handles both stuck-at and timing failures (transition faults and hold time faults). The experimental results based on simulation and silicon units for several products show the effectiveness of the proposed method.

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