Proceedings of the Design Automation & Test in Europe Conference
Latest Publications

TOTAL DOCUMENTS

323

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

3981080114

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Constructing Portable Compiled Instruction-set Simulators-An ADL-driven Approach

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.244006 ◽

2006 ◽

Cited By ~ 21

Author(s):

J. D'Errico ◽

Wei Qin

Keyword(s):

Instruction Set ◽

Instruction Set Simulators

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Dynamic Bit-width Adaptation in DCT: Image Quality versus Computation Energy Trade-off

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243862 ◽

2006 ◽

Cited By ~ 1

Author(s):

Jongsun Park ◽

Jung Hwan Choi ◽

K. Roy

Keyword(s):

Image Quality ◽

Trade Off ◽

Energy Trade

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Parallel co-simulation using virtual synchronization with redundant host execution

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.244001 ◽

2006 ◽

Cited By ~ 5

Author(s):

D. Kim ◽

S. Ha ◽

R. Gupta

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Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.244175 ◽

2006 ◽

Cited By ~ 6

Author(s):

P. Gupta ◽

N.K. Jha ◽

L. Lingappan

Keyword(s):

Cellular Automata ◽

Test Generation ◽

Quantum Cellular Automata ◽

Qca Circuits

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An environment for controlled experiments with in-house sensor networks

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243976 ◽

2006 ◽

Author(s):

V. Handziski ◽

A. Koepke ◽

A. Willig ◽

A. Wolisz

Keyword(s):

Sensor Networks ◽

Controlled Experiments

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Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243897 ◽

2006 ◽

Cited By ~ 4

Author(s):

K.R. Gandhi ◽

N.R. Mahapatra

Keyword(s):

Energy Consumption ◽

Datapath Circuits

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Comfortable Modeling of Complex Reactive Systems

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243970 ◽

2006 ◽

Cited By ~ 2

Author(s):

S. Prochnow ◽

R. von Hanxleden

Keyword(s):

Reactive Systems

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A secure Scan Design Methodology

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.244019 ◽

2006 ◽

Cited By ~ 9

Author(s):

D. Hely ◽

F. Bancel ◽

M.-L. Flottes ◽

B. Rouzeyre

Keyword(s):

Design Methodology ◽

Scan Design

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Statistical timing analysis with path reconvergence and spatial correlations

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243890 ◽

2006 ◽

Cited By ~ 8

Author(s):

Lizheng Zhang ◽

Yuhen Hu ◽

C. Chung-Ping Chen

Keyword(s):

Timing Analysis ◽

Spatial Correlations ◽

Statistical Timing Analysis ◽

Statistical Timing

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A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories

Proceedings of the Design Automation & Test in Europe Conference ◽

10.1109/date.2006.243780 ◽

2006 ◽

Author(s):

P. Daglio

Keyword(s):

Design Flow ◽

Flash Memories ◽

Mixed Signal ◽

Embedded Flash

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Proceedings of the Design Automation & Test in Europe ConferenceLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Constructing Portable Compiled Instruction-set Simulators-An ADL-driven Approach

Dynamic Bit-width Adaptation in DCT: Image Quality versus Computation Energy Trade-off

Parallel co-simulation using virtual synchronization with redundant host execution

Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits

An environment for controlled experiments with in-house sensor networks

Exploiting Data-Dependent Slack Using Dynamic Multi-VDD to Minimize Energy Consumption in Datapath Circuits

Comfortable Modeling of Complex Reactive Systems

A secure Scan Design Methodology

Statistical timing analysis with path reconvergence and spatial correlations

A Complete and Fully Qualified Design Flow for Verification of Mixed-Signal SoC with Embedded Flash Memories

Proceedings of the Design Automation & Test in Europe Conference
Latest Publications