Thin oxide thickness extrapolation from capacitance-voltage measurements

1997 ◽  
Vol 44 (7) ◽  
pp. 1136-1142 ◽  
Author(s):  
S.V. Walstra ◽  
Chih-Tang Sah
Keyword(s):  
Oxide Thickness ◽  
Capacitance Voltage ◽  
Thin Oxide

FABRICATION AND ELECTRICAL PROPERTIES OF Au/PVDF-TrFE/LaZrOx/Si(100) STRUCTURE

2010 ◽  
Vol 24 (22) ◽  
pp. 4203-4208 ◽  
Author(s):  
HUI-SEONG HAN ◽  
GWANG-GEUN LEE ◽  
BYUNG-EUN PARK
Keyword(s):  
Thin Films ◽  
Polyvinylidene Fluoride ◽  
Oxide Thickness ◽  
Voltage Sweep ◽  
Window Width ◽  
Capacitance Voltage ◽  
Coating Method ◽  
Insulator Layers ◽  
Lanthanum Zirconium Oxide ◽  
P Type

Metal-ferroelectric-insulator-semiconductor structure capacitors with a polyvinylidene fluoride trifluoroethylene (75/25) (PVDF-TrFE) ferroelectric and a lanthanum zirconium oxide ( LaZrO x) insulator layers were fabricated on a p-type Si(100) substrate in this work. The thin films were prepared using the spin-coating method. The LaZrO x thin films were crystallized at 750°C for 30 min in an O 2 ambient. Negligible hysteresis was observed from the C–V (capacitance-voltage) characteristic of the LaZrO x/ Si structure. The equivalent oxide thickness (EOT) was about 8.2 nm. Then the PVDF-TrFE film was spin-coated on the LaZrO x/ Si structure. To crystallize the PVDF-TrFE, the structure was annealed at 165°C for 30 min. The memory window width in the C–V curve of the Au/PVDF - TrFE/LaZrO x/ Si structure was about 4 V for a voltage sweep of ±5 V, and the leakage current density was about 10-8 A/cm 2 at 35 kV/cm for a 100-nm-thick film.

Equivalent oxide thickness of a thin oxide interlayer in gate insulator stacks on silicon

2005 ◽  
Vol 86 (19) ◽  
pp. 192901 ◽  
Author(s):  
Feliciano Giustino ◽  
Angelo Bongiorno ◽  
Alfredo Pasquarello
Keyword(s):  
Oxide Thickness ◽  
Gate Insulator ◽  
Equivalent Oxide Thickness ◽  
Thin Oxide

Improvement of Atomic-Layer-Deposited Al2O3/GaAs Interface Quality through a Novel Sulfuration Method

2011 ◽  
Vol 287-290 ◽  
pp. 2327-2331
Author(s):  
Ge Ming Tan ◽  
Qing Qing Sun ◽  
Hong Liang Lu ◽  
Peng Fei Wang ◽  
Shi Jin Ding ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Oxide Thickness ◽  
Gaas Surface ◽  
Interface Quality ◽  
Mos Capacitors ◽  
X Ray ◽  
Native Oxides ◽  
Capacitance Voltage ◽  
Chemical Passivation ◽  
Elemental Arsenic

The absence of stable oxide/GaAs interface greatly holds back the step of GaAs-based MOSFETs fabrication. In this letter, we report on the chemical passivation of n-type GaAs surface by introducing a new sulfuration method. X-ray photon-electron spectroscopy (XPS) analyses indicate that most GaAs native oxides and elemental arsenic (As) can be more effectively removed by treating the GaAs surface in CH3CSNH2solution compared to the traditional (NH4)2S solution. Capacitance-Voltage characteristics of the CH3CSNH2treated MOS capacitors also presents reduced interfacial layer and equivalent oxide thickness which are well consisted with the conclusion obtained by XPS.

Interface and Bulk Oxide Damage Induced by Boron Implantation

1985 ◽  
Vol 45 ◽  
Author(s):  
H. Wong ◽  
N.W. Cheung
Keyword(s):  
Tunneling Current ◽  
Electron Trapping ◽  
Constant Voltage ◽  
Hole Trapping ◽  
Capacitance Voltage ◽  
Boron Implantation ◽  
Thin Oxide ◽  
Oxide Damage

ABSTRACTInvestigations were carried out on the damage of SiO2 and the Si-SiO2 interface induced by boron implantation through polysilicon/SiO2 /p-Si structures with doses up to 1014cm−2 and annealed at 950°C. Using the constant voltage stressing technique, both capacitance-voltage and thin-oxide tunneling current measurements showed that both electron trapping and hole trapping are increased, and that ion-induced electron trapping overcompetes hole trapping for boron doses higher than 5×1013cm−2.

Effects of Arsenic Segregation and Electron Trapping on the Capacitance-Voltage Behavior of Polysilicon and Polycide Gates

1990 ◽  
Vol 182 ◽  
Author(s):  
J. Lin ◽  
S. Batra ◽  
K. Park ◽  
J. Lee ◽  
S. Banerjee ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Electron Trapping ◽  
Dopant Segregation ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Capacitance Voltage ◽  
Higher Temperature ◽  
Amorphous Si ◽  
Mos Structures ◽  
Mos Device

AbstractThis paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.

scholarly journals Определение параметров структур металл-диэлектрик- полупроводник со сверхтонким изолирующим слоем из высокочастотных вольт-фарадных характеристик

2019 ◽  
Vol 53 (1) ◽  
pp. 46
Author(s):  
Е.И. Гольдман ◽  
Н.Ф. Кухарская ◽  
С.А. Левашов ◽  
Г.В. Чучева
Keyword(s):  
Total Concentration ◽  
Oxide Thickness ◽  
Charge Carriers ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Band Bending ◽  
Insulating Layer ◽  
Energy Band Bending ◽  
Capacitance Voltage ◽  
Boundary States

AbstractA simple numerical method for processing the data of the high-frequency capacitance–voltage characteristics of metal–insulator–semiconductor structures is proposed. The approach is based on analyzing the experimental characteristics near the flat-band states, where the charge exchange of surface localized electron states is of little importance compared with changes in the near-boundary charged layer in the semiconductor. The developed technique makes it possible, first, to find the necessary parameters of the semiconductor and insulating layer and, second, to obtain the experimental field dependences of the energy-band bending in the semiconductor and the total concentration of the built-in charge, the charge of boundary states and minority charge carriers at the semiconductor–insulator interface in the range from the flat bands to deep depletion. The technique is well applicable to structures with an ultra-thin insulating layer. On n -Si-based metal–oxide–semiconductor samples with an oxide thickness of 39 Å, experimental approbation of the proposed approach is carried out. The accuracy of the obtained results is 2–3%.

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