Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

This work primarily focuses on the degradation degree of bulk current (IB) for 28 nm stacked high-k (HK) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), sensed and stressed with the channel-hot-carrier test and the drain-avalanche-hot-carrier test, and uses a lifetime model to extract the lifetime of the tested devices. The results show that when IB reaches its maximum, the ratio of VGS/VDS values at this point, in the meanwhile, gradually increases in the tested devices from the long-channel to the short ones, not just located at one-third to one half. The possible ratiocination is due to the ON-current (IDS), in which the short-channel devices provide larger IDS impacting the drain junction and generating more hole carriers at the surface channel near the drain site. In addition, the decrease in IB after hot-carrier stress is not only the increment in threshold voltage VT inducing the decrease in IDS, but also the increment in the recombination rate due to the mechanism of diffusion current. Ultimately, the device lifetime uses Berkley’s model to extract the slope parameter m of the lifetime model. Previous studies have reported m-values ranging from 2.9 to 3.3, but in this case, approximately 1.1. This possibly means that the critical energy of the generated interface state becomes smaller, as is the barrier height of the HK dielectric to the conventional silicon dioxide as the gate oxide.

Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach

We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all “samples” in this ensemble we calculate time-0 currents (i.e., currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e., have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions the distribution of drain currents becomes wider with stress time, in the operating regime drain current variability diminishes. Finally, we show that if random traps are also taken into account, all the obtained trends remain the same.