Effects of Arsenic Segregation and Electron Trapping on the Capacitance-Voltage Behavior of Polysilicon and Polycide Gates

1990 ◽  
Vol 182 ◽  
Author(s):  
J. Lin ◽  
S. Batra ◽  
K. Park ◽  
J. Lee ◽  
S. Banerjee ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Electron Trapping ◽  
Dopant Segregation ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Capacitance Voltage ◽  
Higher Temperature ◽  
Amorphous Si ◽  
Mos Structures ◽  
Mos Device

AbstractThis paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.

SiO2/Si Interfaces Studied by Stm and Hrtem

1990 ◽  
Vol 183 ◽  
Author(s):  
Masaaki Niwa ◽  
Minoru Onoda ◽  
Hiroshi Iwasaki ◽  
Robert Sinclair
Keyword(s):  
Oxide Thickness ◽  
High Energy ◽  
Interface Roughness ◽  
Oxide Interface ◽  
Oxide Interfaces ◽  
Polysilicon Gate ◽  
High Energy Electrons ◽  
Stm Image ◽  
Mos Structures ◽  
Good Agreement

AbstractThe morphology of SiO2/Si interfaces in a semiconductor LOCOS active area grown by several oxidation conditions has been studied, to compare the roughness of the interfaces observed by STM and HRTEM in particular. Samples consisted of typical MOS structures with a polysilicon gate/SiO2/Si(100). Hydrogen terminated Si surfaces were prepared by means of HF dipping for STM observations. The interface roughness of a “dry” oxide observed by HRTEM was slightly larger than that of a “wet” oxide. Good agreement could be found between STM and HRTEM for the wet oxide interfaces. As for the dry oxide interface, it was more difficult to obtain a reproducible STM image than for the wet oxide interface, but the reverse was true for HRTEM. During the HRTEM, high energy electrons damage the sample and reduce the oxide thickness, especially in the wet oxide samples.

A Model of Threshold Voltage in FinFET

2011 ◽  
Vol 216 ◽  
pp. 167-170
Author(s):  
Jian Liu ◽  
Li Li ◽  
X.H. Zhang
Keyword(s):  
Numerical Simulation ◽  
Threshold Voltage ◽  
Doping Concentration ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Threshold Voltage Model

A physics-based threshold voltage model is proposed, according to the electrostatics distribution in Si body of FinFET which is obtained by 2-D numerical simulation. Threshold voltage of FinFET calculated from the model is matched with results of numerical simulation. Influences of polysilicon gate doping concentration, Si body doping concentration, the width and height of Si body and the gate oxide thickness on threshold voltage were investigated. As results,Si body doping concentration, gate doping concentration and the width of Si body have been found to be the most important parameters for the design of threshold voltage of FinFET-like devices.

scholarly journals Study of Interface Charge Densities for ZrO2and HfO2Based Metal-Oxide-Semiconductor Devices

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
N. P. Maity ◽  
Reshmi Maity ◽  
R. K. Thapa ◽  
S. Baishya
Keyword(s):  
Metal Oxide ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Charge Densities ◽  
Interface Charge ◽  
Capacitance Voltage ◽  
P Type ◽  
Mos Structures ◽  
Good Agreement

A thickness-dependent interfacial distribution of oxide charges for thin metal oxide semiconductor (MOS) structures using high-kmaterials ZrO2and HfO2has been methodically investigated. The interface charge densities are analyzed using capacitance-voltage (C-V) method and also conductance (G-V) method. It indicates that, by reducing the effective oxide thickness (EOT), the interface charge densities (Dit) increases linearly. For the same EOT,Dithas been found for the materials to be of the order of 1012 cm−2 eV−1and it is originated to be in good agreement with published fabrication results at p-type doping level of1×1017 cm−3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

1998 ◽  
Vol 19 (9) ◽  
pp. 348-350 ◽  
Author(s):  
Jiunn-Yann Tsai ◽  
Ying Shi ◽  
S. Prasad ◽  
S.W.-C. Yeh ◽  
R. Rakkhit
Keyword(s):  
Gate Oxide ◽  
Oxide Thickness ◽  
Thickness Increase ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness

Effects of Inversion Layer Quantization and Polysilicon Gate Depletion on Tunneling Current of Ultra-Thin SiO2 Gate Material

1999 ◽  
Vol 567 ◽  
Author(s):  
S. Saha ◽  
G. Srinivasan ◽  
G. A. Rezvani ◽  
M. Farr
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Inversion Layer ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Gate Leakage ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
The Impact

ABSTRACTWe have investigated the impact of inversion layer quantization and polysilicon-gate depletion effects on the direct-tunneling gate-leakage current and reliability of ultra-thin silicon-dioxide gate dielectric. The gate-leakage current was measured for nMOSFET devices with gate oxide thickness down to 3 nm. A simulation-based methodology was used to determine the physical oxide thickness from the measured capacitance data, and the corresponding effective gate oxide thickness at inversion was computed from the simulation data obtained with and without the quantum mechanical and polysilicon depletion effects. The simulation results indicate that the effective gate oxide thickness is significantly higher than the physically grown oxide thickness due to inversion layer quantization and polysilicon depletion effects. The increase in oxide thickness is strongly dependent on the supply voltage and is more than 0.6 nm at 1 V. Our data, also, show that in order to maintain a leakage current ≥ 1 A/cm2 for 1 V operation, the effective gate oxide thickness must be ≥ 2.2 nm.

scholarly journals Effect of size and position of gold nanocrystals embedded in gate oxide of SiO2/Si MOS structures

2016 ◽  
Vol 06 (01) ◽  
pp. 1650001 ◽  
Author(s):  
Chaitali Chakraborty ◽  
Chayanika Bose
Keyword(s):  
Oxide Semiconductor ◽  
Internal Electric Field ◽  
Interface Traps ◽  
Gold Nanocrystals ◽  
Simulation Tools ◽  
Voltage Curve ◽  
Capacitance Voltage ◽  
Mos Structures ◽  
Mos Device

The influence of single and double layered gold (Au) nanocrystals (NC), embedded in SiO2 matrix, on the electrical characteristics of metal–oxide–semiconductor (MOS) structures is reported in this communication. The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools. In a single NC-layered MOS structure, the role of NCs is more prominent when they are placed closer to SiO2/Si[Formula: see text]substrate interface than to SiO2/Al–gate interface. In MOS structures with larger NC dots and double layered NCs, the charge storage capacity is increased due to charging of the dielectric in the presence of NCs. Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device. A new phenomenon of smearing out of the capacitance–voltage curve is observed in the presence of dual NC layer indicating generation of interface traps. An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO2/Si interface.

Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

1999 ◽  
Vol 592 ◽  
Author(s):  
Siguang Ma ◽  
Yaohui Zhang ◽  
M. F. Li ◽  
Weidan Li ◽  
J. L. F. Wang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Field Enhancement ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Deep Submicron ◽  
Interface Traps ◽  
Low Field ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Thin Gate Oxide

ABSTRACTIn this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain leakage current caused by plasma charging damage is a function of metal 1 antenna area/length ratio and cell location. Combined with the charge pumping measurements, it is found that gate induced drain leakage current enhancement is mainly due to the plasma induced interface traps. A linear relationship between the gate induced drain leakage and the plasma induced interface trap density is observed within the experimental error. On the other hand, the threshold voltage measurements show that oxide trapped charge has no major contribution to, and no correlation with, the gate induced drain leakage current for thin gate oxide MOSFET devices.

Radiation Hardness for Silicon Oxide and Aluminum Oxide on 4H-SiC

2018 ◽  
Vol 924 ◽  
pp. 229-232 ◽  
Author(s):  
Anders Hallén ◽  
Sethu Saveda Suvanam
Keyword(s):  
Proton Irradiation ◽  
Silicon Oxide ◽  
Positive Charge ◽  
Gate Dielectric ◽  
Radiation Hardness ◽  
Flat Band ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Radiation Hard ◽  
Mos Structures

The radiation hardness of two dielectrics, SiO2and Al2O3, deposited on low doped, n-type 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

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