New High Yield, High Reliability Materials System for Silver Multilayer Construction

1993 ◽  
Vol 10 (1) ◽  
pp. 14-17
Author(s):  
C.R. Pickering ◽  
W.A. Craig ◽  
M.F. Barker ◽  
J. Cocker ◽  
P.C. Donohue ◽  
...  
Keyword(s):  
High Reliability ◽  
High Yield

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

High Reliability Planar InGaAs/InP Photodiodes Made With High Yield by Atmospheric Pressure MOVPE

1988 ◽  
Author(s):  
M. J. Robertson ◽  
C. P. Skrimshire ◽  
S. Ritchie ◽  
S. K. Sargood ◽  
A. W. Nelson ◽  
...  
Keyword(s):  
Atmospheric Pressure ◽  
High Reliability ◽  
High Yield

Assembly challenges in developing 3D IC package with ultra high yield and high reliability

2015 ◽  
Author(s):  
Raghunandan Chaware ◽  
Ganesh Hariharan ◽  
Jeff Lin ◽  
Inderjit Singh ◽  
Glenn O'Rourke ◽  
...  
Keyword(s):  
High Reliability ◽  
High Yield ◽  
3D Ic ◽  
Ic Package

Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator Incorporating High Density TSVs and Interconnects

2012 ◽  
Vol 2012 (1) ◽  
pp. 000984-000990
Author(s):  
Ken Miyairi ◽  
Masahiro Sunohara ◽  
Jean Charbonnier ◽  
Myriam Assous ◽  
Jean-Philippe Bally ◽  
...  
Keyword(s):  
Process Integration ◽  
High Reliability ◽  
Electrical Characterization ◽  
High Density ◽  
High Yield ◽  
Reliability Test ◽  
Organic Substrates ◽  
Resistance Change ◽  
Cte Mismatch

Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers are also promising in terms of high reliability interconnections for large chips due to minimized CTE mismatch compared to standard organic substrates. A silicon interposer including high density TSVs has been successfully processed and fully tested. Process integration has been characterized, electrical results have been analyzed and they will be discussed in this paper. The first half of this paper will focus on integration including several technical challenges such as: 10:1 Aspect Ratio dense TSV of 10μm diameter, damascene metal layers 100,000 25μm diameter micro-bumps per die, and a specific backside redistribution layer, and the electrical data from DC tests achieved after full realization of the silicon interposer. These results show very high yield and a good uniformity among wafers. The later half of this paper will focus on assembly process and reliability test. Conventional mass reflow was performed for each level assembly. As assembly was successfully processed, reliability test which were TC 1000 cycles to check electrical connection on daisy chain and C4 bump, HTS for 1000 hours to observe resistance change on C4 bump and HAST 1000hours to check underfill delamination was performed. All samples passed each reliability test. The results in detail will be discussed in this paper.

Copper, Nickel, and Lead-Free Solder Electroplating Solutions for Pillar and Micro-Pillar Capping Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001417-001437
Author(s):  
Julia Woertink ◽  
Erik Reddington ◽  
Inho Lee ◽  
Yi Qin ◽  
Jonathan Prange ◽  
...  
Keyword(s):  
Flip Chip ◽  
High Reliability ◽  
Interfacial Properties ◽  
Lead Free ◽  
High Yield ◽  
Lead Free Solder ◽  
Barrier Layers ◽  
3D Packaging ◽  
Free Solder ◽  
Electroplated Copper

Control of height-uniformity, morphology, and interfacial properties is critical to achieving high-yield, high-reliability Copper Pillar and Copper Micro-Pillar capped structures for flip-chip and 3D Packaging applications. The plating chemistries selected for electrolytic copper, barrier layer, and lead-free solder deposition significantly affect these properties. A range of copper plating chemistries is evaluated for plating performance and deposit properties for 20um diameter and 75um diameter pillar plating. Height uniformity, pillar shape, surface morphology, and physical properties are compared. These electroplated copper pillars are then evaluated for compatibility with barrier layers and lead-free solder capping. Post-reflow IMC formation, interfacial properties, and micro-voiding phenomena are studied and the effect of the plating chemistry on the overall compatibility of layers in stacked structures is discussed.

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