Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator Incorporating High Density TSVs and Interconnects

2012 ◽  
Vol 2012 (1) ◽  
pp. 000984-000990
Author(s):  
Ken Miyairi ◽  
Masahiro Sunohara ◽  
Jean Charbonnier ◽  
Myriam Assous ◽  
Jean-Philippe Bally ◽  
...  
Keyword(s):  
Process Integration ◽  
High Reliability ◽  
Electrical Characterization ◽  
High Density ◽  
High Yield ◽  
Reliability Test ◽  
Organic Substrates ◽  
Resistance Change ◽  
Cte Mismatch

Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers are also promising in terms of high reliability interconnections for large chips due to minimized CTE mismatch compared to standard organic substrates. A silicon interposer including high density TSVs has been successfully processed and fully tested. Process integration has been characterized, electrical results have been analyzed and they will be discussed in this paper. The first half of this paper will focus on integration including several technical challenges such as: 10:1 Aspect Ratio dense TSV of 10μm diameter, damascene metal layers 100,000 25μm diameter micro-bumps per die, and a specific backside redistribution layer, and the electrical data from DC tests achieved after full realization of the silicon interposer. These results show very high yield and a good uniformity among wafers. The later half of this paper will focus on assembly process and reliability test. Conventional mass reflow was performed for each level assembly. As assembly was successfully processed, reliability test which were TC 1000 cycles to check electrical connection on daisy chain and C4 bump, HTS for 1000 hours to observe resistance change on C4 bump and HAST 1000hours to check underfill delamination was performed. All samples passed each reliability test. The results in detail will be discussed in this paper.

CMOS-Compatible Through Silicon Vias for 3D Process Integration

2006 ◽  
Vol 970 ◽  
Author(s):  
Cornelia K. Tsang ◽  
Paul S. Andry ◽  
Edmund J. Sprogis ◽  
Chirag S. Patel ◽  
Bucknell C. Webb ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Process Integration ◽  
Three Dimensional ◽  
High Density ◽  
High Yield ◽  
Large Area ◽  
Process Flow ◽  
Through Silicon Via ◽  
Through Silicon Vias ◽  
Silicon Vias

ABSTRACTAs the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150μm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated.

Electrical Characterization of 3C-SiC Lateral MOSFETs Fabricated on Heteroepitaxial Films Including High Density of Defects

2015 ◽  
Vol 821-823 ◽  
pp. 733-736 ◽  
Author(s):  
Yukimune Watanabe ◽  
Noriyasu Kawana ◽  
Tsuyoshi Horikawa ◽  
Kiichi Kamimura
Keyword(s):  
Gate Voltage ◽  
Light Emission ◽  
Electrical Characterization ◽  
Charge Trapping ◽  
Drain Current ◽  
High Density ◽  
Electrical Characteristics ◽  
Voltage Curve ◽  
Emission Light

We have fabricated lateral MOSFETs on heteroepitaxial 3C-SiC films included high density of defects. Electrical characteristics of 3C-SiC MOSFETs and their temperature dependence were measured to discuss effects of defects on the electrical characteristics. A field effect mobility of 156 cm2/Vs was obtained at room temperature. After applying a drain voltage of 10 V or higher, the drain current - gate voltage curve shifted toward the positive gate voltage. This shift was caused mainly by the charge trapping in the gate oxide. The light emission was observed on the surface of the active MOSFET. The spatial distribution of the emission light from MOSFETs indicated that the charge was generated at the source edge of the gate channel.

Overcoming the Challenges of Parallel, SRAM Shorts Test Structures with EBIRCH

2018 ◽  
Author(s):  
Noor Jehan Saujauddin ◽  
Lloyd Smith ◽  
Randy Newkirk ◽  
Kevin Davidson ◽  
Gregory M. Johnson ◽  
...  
Keyword(s):  
Accurate Determination ◽  
Electrical Characterization ◽  
Advanced Technology ◽  
Massively Parallel ◽  
Resistance Change ◽  
Design Elements ◽  
Time Required ◽  
Technology Nodes

Abstract Massively parallel test structures, based on looking for shorts between certain design elements in the SRAM cells, are becoming increasingly relied upon in yield characterization. The localization of electrical shorts in these structures has posed significant challenges in advanced technology nodes, due to the size, and design complexity. Several of the traditional methods (nanoprobing, OBIRCH, etc.) are shown to be inadequate to find defects in SRAM cells, either due to resolution, or time required. In recent years, the Electron Beam Induced Resistance Change (EBIRCH) technique has increasingly been utilized for failure analysis. Combining EBIRCH with other techniques, such as SEM based nanoprobing system and PVC, allows not only direct electrical characterization of suspicious bridging sites but also allows engineers to pinpoint the exact location of defects with SEM resolution. This paper will demonstrate the several cases where SRAM-like test structures provided extreme challenges, and EBIRCH was the key technique towards finding the fail. A node to node, node to wordline, and ground-ground contact fails are presented. A combination of EBIRCH with the more traditional techniques in advanced technology node is key to timely and accurate determination of shorting mechanisms in our test structures.

DIELECTRIC FORMATION AND ELECTRICAL CHARACTERIZATION OF SINTERED TANTALUM SLUGS

2007 ◽  
Vol 21 (02n03) ◽  
pp. 123-128 ◽  
Author(s):  
R. GOVINDAIAH ◽  
T. BALAJI ◽  
ARBIND KUMAR ◽  
N. PARASURAM ◽  
Y. PURUSHOTHAM ◽  
...  
Keyword(s):  
Leakage Current ◽  
High Reliability ◽  
Chemical Properties ◽  
Electrical Characterization ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Lcr Meter ◽  
Physical And Chemical ◽  
And Chemical Properties

The present electronic industry requires capacitors having high capacitance with lower volume and space, high reliability and low leakage current. The solid tantalum capacitor ideally meets such requirements. In the present paper, the electrical characterization of tantalum anodes prepared from sodium reduced tantalum powder has been described. The capacitance, DC leakage current are measured for tantalum anodes made with different particle sizes of powders using the LCR Meter and DC Leakage Tester and compared with the physical and chemical properties. Interestingly, it was found that the DC leakage current decreases with decrease in particle size on contrary to the surface area. Besides, a trade-off appears imminent to establish the formation voltage and DC leakage current relationship.

Electrical characterization of POLYHIC, a high density, high frequency, interconnection and packaging medium for digital circuits

2003 ◽  
Author(s):  
J.L. Brandner ◽  
C.C. Faudskar ◽  
M.E. Lindenmeyer ◽  
S.R. Hofmann ◽  
D.B. Buchholz ◽  
...  
Keyword(s):  
High Frequency ◽  
Digital Circuits ◽  
Electrical Characterization ◽  
High Density
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