Assembly challenges in developing 3D IC package with ultra high yield and high reliability

2015 ◽  
Author(s):  
Raghunandan Chaware ◽  
Ganesh Hariharan ◽  
Jeff Lin ◽  
Inderjit Singh ◽  
Glenn O'Rourke ◽  
...  
Keyword(s):  
High Reliability ◽  
High Yield ◽  
3D Ic ◽  
Ic Package

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

New High Yield, High Reliability Materials System for Silver Multilayer Construction

1993 ◽  
Vol 10 (1) ◽  
pp. 14-17
Author(s):  
C.R. Pickering ◽  
W.A. Craig ◽  
M.F. Barker ◽  
J. Cocker ◽  
P.C. Donohue ◽  
...  
Keyword(s):  
High Reliability ◽  
High Yield

Analytical and finite element methodology modeling of the thermal management of 3D IC with through silicon via

2016 ◽  
Vol 28 (4) ◽  
pp. 177-187
Author(s):  
Mei-Ling Wu ◽  
Jia-Shen Lan
Keyword(s):  
Heat Source ◽  
Thermal Resistance ◽  
Analytical Model ◽  
Network Model ◽  
Temperature Increase ◽  
3D Ic ◽  
Spreading Resistance ◽  
Content Type ◽  
Silicon Chips ◽  
Ic Package

Purpose This paper aims to develop the thermal resistance network model based on the heat dissipation paths from the multi-die stack to the ambient and takes into account the composite effects of the thermal spreading resistance and one-dimensional (1D) thermal resistance. The thermal spreading resistance comprises majority of the thermal resistance when heat flows in the horizontal direction of a large plate. The present study investigates the role of determining the temperature increase compared to the thermal resistances intrinsic to the 3D technology, including the thermal resistances of bonding layers and through silicon vias (TSVs). Design/methodology/approach This paper presents an effective method that can be applied to predict the thermal failure of the heat source of silicon chips. An analytical model of the 3D integrated circuit (IC) package, including the full structure, is developed to estimate the temperature of stacked chips. Two fundamental theories are used in this paper – Laplace’s equation and the thermal resistance network – to calculate 1D thermal resistance and thermal spreading resistance on the 3D IC package. Findings This paper provides a comprehensive model of the 3D IC package, thus improving the existing analytical approach for predicting the temperature of the heat source on the chip for the 3D IC package. Research limitations/implications Based on the aforementioned shortcomings, the present study aims to determine if the use of an analytical resistance model would improve the handling of a temperature increase on the silicon chips in a 3D IC package. To achieve this aim, a simple rectangular plate is utilized to analyze the temperature of the heat source when applying the heat flux on the area of the heat source. Next, the analytical model of a pure plate is applied to the 3D IC package, and the temperature increase is analyzed and discussed. Practical implications The main contribution of this paper is the use of a simple concept and a theoretical resistance network model to improve the current understanding of thermal failure by redesigning the parameters or materials of a printed circuit board. Social implications In this paper, an analytical model of a 3D IC package was proposed based on the calculation of the thermal resistance and the analysis of the network model. Originality/value The aim of this work was to estimate the mean temperature of the silicon chips and understand the heat convection paths in the 3D IC package. The results reveal these phenomena of the complete structure, including TSV and bump, and highlight the different thermal conductivities of the materials used in creating the 3D IC packages.

High Reliability Planar InGaAs/InP Photodiodes Made With High Yield by Atmospheric Pressure MOVPE

1988 ◽  
Author(s):  
M. J. Robertson ◽  
C. P. Skrimshire ◽  
S. Ritchie ◽  
S. K. Sargood ◽  
A. W. Nelson ◽  
...  
Keyword(s):  
Atmospheric Pressure ◽  
High Reliability ◽  
High Yield

A comprehensive reliability study on a CoWoS 3D IC package

2015 ◽  
Author(s):  
Ganesh Hariharan ◽  
Raghunandan Chaware ◽  
Inderjit Singh ◽  
Jeff Lin ◽  
Laurene Yip ◽  
...  
Keyword(s):  
Reliability Study ◽  
3D Ic ◽  
Comprehensive Reliability ◽  
Ic Package

Reliability evaluation of a CoWoS-enabled 3D IC package

2013 ◽  
Author(s):  
Bahareh Banijamali ◽  
Chien-Chia Chiu ◽  
Cheng-Chieh Hsieh ◽  
Tsung-Shu Lin ◽  
Clark Hu ◽  
...  
Keyword(s):  
Reliability Evaluation ◽  
3D Ic ◽  
Ic Package
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