The influence of silicon heat treatments on the minority carrier generation and the dielectric breakdown in MOS structures

1974 ◽  
Vol 3 (2) ◽  
pp. 579-599 ◽  
Author(s):  
J. M. Green ◽  
C. M. Osburn ◽  
T. O. Sedgwick
Keyword(s):  
Minority Carrier ◽  
Dielectric Breakdown ◽  
Heat Treatments ◽  
Carrier Generation ◽  
Mos Structures

Majority- and minority-carrier lifetime in MOS structures

1975 ◽  
Vol 18 (12) ◽  
pp. 1115-1122 ◽  
Author(s):  
G. Baccarani ◽  
C.A. Baffoni ◽  
M. Rudan ◽  
G. Spadini
Keyword(s):  
Carrier Lifetime ◽  
Minority Carrier ◽  
Minority Carrier Lifetime ◽  
Mos Structures

The Role of Metallic Impurities in the Field-Enhanced Carrier Generation in MOS Structures

1996 ◽  
Vol 154 (2) ◽  
pp. 599-605 ◽  
Author(s):  
P. Peykov ◽  
T. Diaz ◽  
H. Juárez ◽  
R. Castanedo
Keyword(s):  
Carrier Generation ◽  
Mos Structures ◽  
Metallic Impurities

Minority‐carrier generation inn‐InP/SiO2capacitors

1979 ◽  
Vol 35 (1) ◽  
pp. 86-88 ◽  
Author(s):  
J. Stannard ◽  
R. L. Henry
Keyword(s):  
Minority Carrier ◽  
Carrier Generation

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

2014 ◽  
Vol 778-780 ◽  
pp. 595-598 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Oxide Deposition ◽  
Mos Structures ◽  
Field Strengths

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Theoretical Analysis of the Minority Carrier Lifetime in a Multicrystalline Wafer with Spatially Varying Defect Distribution

1998 ◽  
Vol 510 ◽  
Author(s):  
Bhushan Sopori ◽  
Wei Chen ◽  
N. M. Ravindra
Keyword(s):  
Carrier Lifetime ◽  
Minority Carrier ◽  
Weighted Average ◽  
Minority Carrier Lifetime ◽  
Carrier Generation ◽  
Average Value ◽  
Dimensional Modeling ◽  
Solar Cell Fabrication ◽  
Cell Fabrication ◽  
Spatially Varying

AbstractMulticrystalline Si (mc-Si) wafers, used for the commercial solar cell fabrication, have spatial nonuniformities in the material properties that cause strong variations in the minority carrier lifetime, τ. We present the results of two-dimensional modeling to show carrier generation, recombination and transport in such a material. These results are used to infer measurement conditions that can yield meaningful spatially weighted average value of τ.

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