Dielectric breakdown induced by sodium in MOS structures

1973 ◽  
Vol 44 (1) ◽  
pp. 527-528 ◽  
Author(s):  
T. H. DiStefano
Keyword(s):  
Dielectric Breakdown ◽  
Mos Structures

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

2014 ◽  
Vol 778-780 ◽  
pp. 595-598 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Breakdown Field ◽  
Static Capacitance ◽  
Capacitance Voltage ◽  
Oxide Deposition ◽  
Mos Structures ◽  
Field Strengths

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

2015 ◽  
Vol 821-823 ◽  
pp. 753-756 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Martin Rambach ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Inert Gas ◽  
Breakdown Field ◽  
Wafer Surface ◽  
Mos Devices ◽  
Uniform Current ◽  
Thin Gate Oxide ◽  
Mos Structures

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

2013 ◽  
Vol 740-742 ◽  
pp. 691-694 ◽  
Author(s):  
Christian T. Banzhaf ◽  
Michael Grieb ◽  
Achim Trautmann ◽  
Anton J. Bauer ◽  
Lothar Frey
Keyword(s):  
Silicon Dioxide ◽  
Dielectric Breakdown ◽  
Interface State ◽  
Oxide Semiconductor ◽  
Breakdown Field ◽  
Flat Band ◽  
Mos Devices ◽  
State Densities ◽  
Mos Structures

This study focuses on the characterization of silicon dioxide (SiO2) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (DIT) of 1*1011cm-2eV-1under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Gate Electrode Effects On Dielectric Breakdown Of SiO2

1996 ◽  
Vol 446 ◽  
Author(s):  
Akira Toriumi ◽  
Yuichiro Mitani ◽  
Hideki Satake
Keyword(s):  
Network Structure ◽  
Electrode Material ◽  
Silicon Substrate ◽  
Dielectric Breakdown ◽  
Oxide Thickness ◽  
Experimental Results ◽  
Gate Electrode ◽  
Impurity Doping ◽  
Hole Current ◽  
Mos Structures

AbstractWe discuss the gate electrode effects on SiO2 degradation in MOS structures. The gate electrode material was poly‐silicon, but the impurity doping procedure was varied in terms of species and concentrations. First, the origin of the substrate hole current observed in n‐MOSFETs, by injecting electrons from the silicon substrate, is discussed in terms of oxide thickness and gate electrode doping species, because the dielectric breakdown is closely related to the total hole fluence in the oxide. The effects of the gate electrode on the oxide network structure and on the Si/SiO2 interface are also experimentally investigated. Finally, the experimental results obtained for Qbd of different gate electrode MOSFETs are shown, including the polarity dependence of Qbd. Furthermore, the percolation analysis to explain the polarity dependence is introduced, since the dielectric breakdown process is really stochastic.

Oxide Degradation Resulting from Photoresist Ashing

1993 ◽  
Vol 309 ◽  
Author(s):  
P. I. Mikulan ◽  
T. T. Koo ◽  
O. O. Awadelkarim ◽  
S. J. Fonash ◽  
T. Ta ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Deep Level ◽  
Electrical Characterization ◽  
Si Substrate ◽  
Time Dependent Dielectric Breakdown ◽  
Oxide Degradation ◽  
Current Voltage ◽  
Transient Spectroscopy ◽  
Mos Structures

AbstractIn this study, possible SiO2 damage that could result from several different photoresist ashing techniques has been assessed using patterned photoresist over blanket oxides. The types of ashing systems used were RF power (RF), upstream ozone generator (Upstream) and two microwave power reactors (Microwave 1 and Microwave 2). Aluminum capacitors were evaporated on the samples after the ashing for oxide evaluation. Electrical characterization of these MOS structures included capacitance verses voltage and time dependent dielectric breakdown measurements. We also looked for Si substrate damage in these samples using deep level transient spectroscopy and Schottky barrier current-voltage measurements. This characterization showed oxide damage varied widely with ashing tool. In all cases, however, there was no significant Si substrate damage.

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