2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)
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Novel Self-Convergent Scheme Logic-Process-Based Multilevel/Analog EEPROM Memory

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.29 ◽

2005 ◽

Author(s):

Kung-Hong Lee ◽

Shih-Chen Wang ◽

Ya-Chin King

Keyword(s):

Logic Process

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Full-Speed Field Programmable Memory BIST Supporting Multi-level Looping

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.25 ◽

2005 ◽

Author(s):

Xiaogang Du ◽

N. Mukherjee ◽

Wu-Tung Cheng ◽

S.M. Reddy

Keyword(s):

Field Programmable ◽

Full Speed ◽

Multi Level

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DFT Techniques for Memory Macro with Built-In ECC

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.19 ◽

2005 ◽

Cited By ~ 3

Author(s):

K. Kushida ◽

N. Otsuka ◽

O. Hirabayashi ◽

Y. Takeyama

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A 1GHz Embedded DRAM Macro and Fully Programmable BIST with At-Speed Bitmap Capability

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.5 ◽

2005 ◽

Author(s):

V. Lines ◽

R. McKenzie ◽

Hak-June Oh ◽

H. Pyeon ◽

M. Dunn ◽

...

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A Nor-Type MLC ROM with Novel Sensing Scheme for Embedded Applications

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.11 ◽

2005 ◽

Author(s):

Star Sung ◽

T. Chang ◽

JueiLung Chen

Keyword(s):

Embedded Applications

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FSM-Based Programmable Memory BIST with Macro Command

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.24 ◽

2005 ◽

Cited By ~ 5

Author(s):

Po-Chang Tsai ◽

Sying-Jyan Wang ◽

Feng-Ming Chang

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Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.21 ◽

2005 ◽

Author(s):

Chung-Hsien Hua ◽

Tung-Shuan Cheng ◽

Wei Hwang

Keyword(s):

Distributed Data ◽

Power Gating ◽

Data Retention ◽

Embedded Sram

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An Error Detection and Correction Scheme for RAMs with Partial-Write Function

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.16 ◽

2005 ◽

Cited By ~ 2

Author(s):

Jin-Fu Li ◽

Yu-Jane Huang

Keyword(s):

Error Detection ◽

Correction Scheme ◽

Error Detection And Correction

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A High Speed BIST Architecture for DDR-SDRAM Testing

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.9 ◽

2005 ◽

Cited By ~ 1

Author(s):

Sheng-Chih Shen ◽

Hung-Ming Hsu ◽

Yi-Wei Chang ◽

Kuen-Jong Lee

Keyword(s):

High Speed

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Dielectric Tunnel Parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM Applications

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05) ◽

10.1109/mtdt.2005.20 ◽

2005 ◽

Author(s):

S.C. Li ◽

J.M. Lee ◽

M.F. Shu ◽

J.P. Su ◽

T.-H. Wu

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2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Novel Self-Convergent Scheme Logic-Process-Based Multilevel/Analog EEPROM Memory

Full-Speed Field Programmable Memory BIST Supporting Multi-level Looping

DFT Techniques for Memory Macro with Built-In ECC

A 1GHz Embedded DRAM Macro and Fully Programmable BIST with At-Speed Bitmap Capability

A Nor-Type MLC ROM with Novel Sensing Scheme for Embedded Applications

FSM-Based Programmable Memory BIST with Macro Command

Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM

An Error Detection and Correction Scheme for RAMs with Partial-Write Function

A High Speed BIST Architecture for DDR-SDRAM Testing

Dielectric Tunnel Parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM Applications

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)
Latest Publications