Novel Self-Convergent Scheme Logic-Process-Based Multilevel/Analog EEPROM Memory

Author(s):  
Kung-Hong Lee ◽  
Shih-Chen Wang ◽  
Ya-Chin King
Keyword(s):  
Author(s):  
Dinesh Somasekhar ◽  
Yibin Ye ◽  
Paolo Aseron ◽  
Shih-Lien Lu ◽  
Muhammad Khellah ◽  
...  
Keyword(s):  

2012 ◽  
Vol 2012 (1) ◽  
pp. 000018-000022
Author(s):  
S.Q. Gu ◽  
D.W. King ◽  
V. Ramachandran ◽  
B. Henderson ◽  
U. Ray ◽  
...  

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices. In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.


2016 ◽  
Vol 12 (2) ◽  
pp. 18-38 ◽  
Author(s):  
Erich Ortner ◽  
Marco Mevius ◽  
Peter Wiedmann ◽  
Florian Kurz

Nowadays, the number of human to application system interactions is dramatically increasing. For instance, citizens interact with the help of the internet to organize meetings spontaneously. Furthermore, standards such as Business Process Model and Notation (BPMN) and the Decision Modeling Notation (DMN) allow the creation of graphical models to document the (interaction) processes. Moreover, simulations and automations can be set up to encounter new technical challenges. Smart Cities aim at enabling their citizens to use these digital services. However, looking beyond technology, there is still a significant lack of interaction and support between “normal” citizens and the public administration. This article introduces an approach, which describes the design of enhanced interactional applications for decision support in Smart Cities based on Dialogical Logic process patterns. The authors demonstrate the approach with the help of a use case concerning a budgeting scenario as well as a summary and outlook on further research.


Author(s):  
Nayeth I. Alcivar ◽  
Louis Sanzogni ◽  
Luke Houghton

Information Systems (IS) research continues to contribute to a long list of technology adoption factors from many studies conducted outside the Latin American (LAT) nations. These investigations fail to appropriate the context of IS adoption in LAT. This fail is mainly due to the geographical scope of existing studies. Those aimed at North America for example, are out of context regarding a diverse technological approach when applied to LAT. Further, uncertainty and an inability to predict outcomes of technology adoption, create variances in results because the local contexts are not considered. The reasons for this are unclear from existing studies. To detailed explore this problem further, a Qualitative Comparative Analysis (QCA) was applied to LAT economies, expecting to assess a refined set of drivers from existing technology adoption studies. A Fuzzy Logic process was used to refine these drivers. The research found that fourteen themes are candidates for future study purposes. The drivers provide LAT stakeholders, as well as actors from other emerging economies, with a contextual frame that can be the basis for adopting technology more meaningfully within these nations


1996 ◽  
Vol 122 (6) ◽  
pp. 484-492 ◽  
Author(s):  
Mark T. Yin ◽  
Michael K. Stenstrom

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