11th International Symposium on High-Performance Computer Architecture
Latest Publications

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(FIVE YEARS 0)

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(FIVE YEARS 0)

Published By IEEE

0769522750

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.15 ◽

2005 ◽

Cited By ~ 15

Author(s):

Xuning Chen ◽

L.-S. Peh ◽

Gu-Yeon Wei ◽

Yue-Kai Huang ◽

P. Prucnal

Keyword(s):

Design Space ◽

Networked Systems

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Chip Multithreading: Opportunities and Challenges

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.10 ◽

2005 ◽

Cited By ~ 70

Author(s):

L. Spracklen ◽

S.G. Abraham

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Tapping ZettaRAM™ for Low-Power Memory Systems

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.35 ◽

2005 ◽

Cited By ~ 2

Author(s):

R.K. Venkatesan ◽

A.S. AL-Zawawi ◽

E. Rotenberg

Keyword(s):

Low Power ◽

Memory Systems

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An Efficient Programmable 10 Gigabit Ethernet Network Interface Card

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.6 ◽

2005 ◽

Cited By ~ 26

Author(s):

P. Willmann ◽

Hyong-youb Kim ◽

S. Rixner ◽

V.S. Pai

Keyword(s):

Network Interface ◽

Gigabit Ethernet ◽

Interface Card ◽

Ethernet Network ◽

10 Gigabit Ethernet

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A Unified Compressed Memory Hierarchy

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.4 ◽

2005 ◽

Cited By ~ 53

Author(s):

E.G. Hallnor ◽

S.K. Reinhardt

Keyword(s):

Memory Hierarchy

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Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.42 ◽

2005 ◽

Cited By ~ 3

Author(s):

A. Jaleel ◽

B. Jacob

Keyword(s):

Negative Effects

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SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.29 ◽

2005 ◽

Cited By ~ 40

Author(s):

Feng Qin ◽

Shan Lu ◽

Yuanyuan Zhou

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Microarchitectural Wire Management for Performance and Power in Partitioned Architectures

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.21 ◽

2005 ◽

Cited By ~ 25

Author(s):

R. Balasubramonian ◽

N. Muralimanohar ◽

K. Ramani ◽

V. Venkatachalapathy

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Multithreaded Value Prediction

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.22 ◽

2005 ◽

Cited By ~ 11

Author(s):

N. Tuck ◽

D.M. Tullsen

Keyword(s):

Value Prediction

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The Soft Error Problem: An Architectural Perspective

11th International Symposium on High-Performance Computer Architecture ◽

10.1109/hpca.2005.37 ◽

2005 ◽

Cited By ~ 201

Author(s):

S.S. Mukherjee ◽

J. Emer ◽

S.K. Reinhardt

Keyword(s):

Soft Error ◽

Architectural Perspective

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11th International Symposium on High-Performance Computer ArchitectureLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems

Chip Multithreading: Opportunities and Challenges

Tapping ZettaRAM™ for Low-Power Memory Systems

An Efficient Programmable 10 Gigabit Ethernet Network Interface Card

A Unified Compressed Memory Hierarchy

Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions

SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs

Microarchitectural Wire Management for Performance and Power in Partitioned Architectures

Multithreaded Value Prediction

The Soft Error Problem: An Architectural Perspective

11th International Symposium on High-Performance Computer Architecture
Latest Publications