An Efficient Programmable 10 Gigabit Ethernet Network Interface Card

2005 ◽  
Author(s):  
P. Willmann ◽  
Hyong-youb Kim ◽  
S. Rixner ◽  
V.S. Pai
Keyword(s):  
Network Interface ◽  
Gigabit Ethernet ◽  
Interface Card ◽  
Ethernet Network ◽  
10 Gigabit Ethernet

scholarly journals Design and Simulation of an Optical Gigabit Ethernet Network

2010 ◽  
Vol 18 (3) ◽  
pp. 46-61
Author(s):  
Omar Ahmed Yousif ◽  
Salah A. Jaro Alabady
Keyword(s):  
Gigabit Ethernet ◽  
Ethernet Network

scholarly journals Highly scalable intelligent sensory application and time domain matrix for safety-critical system design

2018 ◽  
Vol 14 (4) ◽  
pp. 155014771774110
Author(s):  
Taikyeong Ted Jeong
Keyword(s):  
Fault Detection ◽  
Detection Algorithm ◽  
Network Interface ◽  
Critical System ◽  
Communication Architecture ◽  
Interface Card ◽  
Safety Critical ◽  
Verification Methods ◽  
Communication Architectures ◽  
And Performance

The designs of highly scalable intelligent sensory application—Ethernet-based communication architectures—are moving toward the integration of a fault recovery and fault-detection algorithm on the automotive industry. In particular, each port on the same network interface card design is required to provide highly scalable and low-latency communication. In this article, we present a study of intelligent sensory application for the Ethernet-based communication architecture and performance of multi-port configuration which is mainly used in safety-enhanced application such as automotive, military, finance, and aerospace, in other words, safety-critical applications. Our contributions and observations on the highly scalable intelligent behavior: (1) proposed network interface card board design scheme and architecture with multi-port configuration are a stable network configuration; (2) timing matrix is defined for fault detection and recovery time; (3) experimental and related verification methods by cyclic redundancy check between client–server and testing platform provide comparable results to each port configurations; and (4) application program interface–level algorithm is defined to make network interface card ready for fault detection.

Implementation of CRC in 10-Gigabit Ethernet Based on FPGA

2014 ◽  
Vol 599-601 ◽  
pp. 1548-1552
Author(s):  
Bin Li ◽  
Zhi Ping Huang ◽  
Shao Jing Su ◽  
Jun Peng Hu
Keyword(s):  
Traditional Method ◽  
Environmental Constraints ◽  
Data Input ◽  
Gigabit Ethernet ◽  
Parallel Data ◽  
Quartus Ii ◽  
Parallel Input ◽  
10 Gigabit Ethernet

This paper describes the algorithm principle of CRC-32 codes, and then proposes multiple bits parallel input to achieve CRC-32 checksum on the basis of the principle. To design modules using VHDL language in Quartus II environment based on Altera’s EP4SGX230KF40C2 chip. Compared to traditional method of serial and 8 bits parallel data input, implementation of the program integrates 16, 32 and 64 bits parallel data input modes, the user can select the appropriate modules according to their needs and environmental constraints, which will greatly enhance the ability to adapt to the system and meet the needs of a variety of environments.

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