1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

Gate voltage-dependent magnetoresistance of Zn0.8Co0.2O:H

The magnetoresistance (MR) of ZnCoO:H was measured at 7 K to verify the MR dependency on carrier density. It was found that MR increased with negative gate voltage. This increase in MR is not caused by an increase in pMR, but by a decrease in nMR.

Nonvolatile memories based on AlOx embedded ZrHfO high-k gate dielectric

ABSTRACTMOS capacitors with the ZrHfO/AlOx/ZrHfO high-k gate dielectric stack were prepared and characterized for memory functions. The device prefers to trap holes, i.e., under the negative gate voltage, rather than electrons, i.e., under the positive voltage. The hole-trapping process is time and voltage dependent. The weakly trapped holes are quickly released upon the remove of the stress voltage. However, more than 30% of the originally trapped holes can be retained in the device after 10 years. The AlOx embedded ZrHfO high-k stack is a suitable gate dielectric structure for nonvolatile memories.