Impact Isolation Through the Use of Compliant Interconnects for Microelectronic Packages

First-level and second-level compliant interconnect structures are being pursued in universities and industries to accommodate the differential displacement induced by the coefficient of thermal expansion mismatch between the die and the substrate or between the substrate and the board. The compliant interconnects mechanically decouple the die from the substrate or the substrate from the board, and thus reduce the thermally induced stresses in the assembly. This paper presents drop-test experimental and simulation data for scaled-up prototype of compliant interconnects. The simulations were based on Input-G method and performed using ANSYS® finite element software for varying drop heights. In parallel to the simulations, scaled-up compliant polymer interconnects sandwiched between a polymer die and a polymer substrate were fabricated using three-dimensional (3D) printing, and this fabrication provides a quick low-cost alternative to cleanroom fabrication. The prototype of the assembly was subjected to drop tests from varying drop heights. The response of the assembly during drop testing was captured using strain gauges and an accelerometer mounted on the prototype. The data from the experiments were compared with the predictions from the simulations. Based on such simulations, significant insight into the behavior of compliant interconnects under impact loading was obtained, which could be used for reliable design of compliant interconnect under impact loading. Both the experimental and simulation data reveal that the compliant interconnects are able to reduce the strains that transfer from substrate to die by one-order.

Application of transient liquid phase sintering (TLPS) interconnect material for high temperature Pb-free RoHS compliant MLCC lead attachment

Transient Liquid Phase Sintering is a process that provides high temperature Pb-free RoHS compliant interconnect solutions that exceed the high temperature capabilities of Pb-Sn solders. KEMET, working in collaboration with Ormet Circuits Inc. has successfully applied Ormet's TLPS technology to a line of Leaded Multi-layer Ceramic Capacitors (MLCC) components for high temperature applications. The material is Pb-free, RoHS compliant and able to withstand process and operating temperatures > 400°C while having initial processing temperatures of less than 300°C. Potential applications for TLPS are in the automotive, aerospace, oil, gas, and geothermal exploration industries where electronics are being exposed to higher operating temperatures and require robust interconnects capable of withstanding harsh environments.

Design and fabrication of MEMS-type compliant overhang flip-chip interconnect for RF applications

With the increase of I/O density and scaling of interconnects, conventional solder ball interconnects are required to be made smaller. As a result, the reliability of the conventional solder ball flip-chip interconnects worsens. One method to mitigate this issue is by using underfill. However, underfill undermines the reworkability of the solder joints and is challenging to apply when the gap between chip and substrate is small. Another approach to enhance the reliability is to use taller solder ball interconnects, which is however usually more costly. Instead of using conventional solder ball interconnects, compliant interconnects have also been researched in the past few decades to mitigate the reliability issue. The use of compliant structures can compensate for the coefficient of thermal expansion (CTE) mismatch between a Si chip and an organic substrate. In this work, we present the design and fabrication of MEMS-type compliant overhang flip-chip interconnects. The structures are placed at the end of a coplanar waveguide (CPW) as interconnects between CPWs to research their performance at radio frequency (RF). A micro-fabrication process was adopted to build the interconnects. The CPWs are fabricated using conventional e-beam deposition followed by photolithography and then copper electroplating. The compliant overhangs were fabricated on top of a dome of reflowed photoresist on the CPWs to form a curved shape. The reflow and hard bake of the photoresist requires a process temperature of above 220 °C, which is similar to the reflow temperature of a Sn-Ag-Cu (SAC) solder. Therefore we believe our process is compatible with SAC solder processing infrastructures in terms of process temperature. The fabricated structures show high yield and uniformity. Due to the use of a micro-fabrication based process, the structures have the potential to be scaled and be compatible to wafer level packaging. The CPWs were then flip-chip bonded with the compliant interconnect as transitions. The RF performance of the interconnects up to 50 GHz will be presented.

Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects

This paper presents a study on a dual-path compliant interconnect design which attempts to improve the balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Implementation of this interconnect technology can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermomechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermomechanical reliability of a dual-path compliant interconnect.

Migration to FC in the Wireless Application Space and Associated Challenges

Summary: Expanding wireless application areas will continue to drive increased semiconductor demand. Consumer demand for increased features/ capability is driving mobile wireless prodcut demand - smaller, sleeker, more affordable devices. Innovative technology scaling is required to meet challenges of low cost, low power and smaller form factors. Co-design of architecture, design, silicon and packaging are required to solve issues with transition to flip chip due to: non-compliant interconnect (pb-free and Cu pillar); mechanically weak dielectrics in die; pressure to shrink package height and x,y dimensions; control co-planarity and high temperature warpage.

Parallel-Path Compliant Structures as Electrical Interconnects

The coefficient of thermal expansion (CTE) mismatch between a die and an organic substrate generates high stresses in the die when underfilled solder bumps are used. These high stresses could crack or delaminate low-K dielectric materials in the next-generation flip-chip devices. In addition to such on-chip failures, the solder interconnects could fail due to thermo-mechanical fatigue, especially when the interconnect dimensions are scaled down to meet fine-pitch requirements. To address these reliability issues, compliant interconnects have been proposed to alleviate the thermo-mechanical stresses in the chip assembly. Some of the challenges to be addressed with compliant interconnects are: higher electrical parasitic compared to solder bumps, cost-effective fabrication, and high-yield, fine-pitch assembly process. This paper presents a study on a parallel-path compliant interconnect design which attempts to balance between mechanical compliance and electrical parasitics by using multiple electrical paths in place of a single electrical path. The high compliance of the parallel-path compliant interconnect structure will ensure the reliability of low-K dies. Also, these interconnects can be cost effective by using a wafer-level process and by eliminating the underfill process. Although an underfill is not required for thermo-mechanical reliability purposes, an underfill may be used for reducing contamination and oxidation of the interconnects and also to provide additional rigidity against mechanical loads. Therefore, this paper also examines the role of an underfill on the thermo-mechanical reliability of a parallel-path compliant interconnect.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.