Cavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication

Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

A Resonant Pressure Microsensor with a Wide Pressure Measurement Range

This paper presents a resonant pressure microsensor with a wide range of pressure measurements. The developed microsensor is mainly composed of a silicon-on-insulator (SOI) wafer to form pressure-sensing elements, and a silicon-on-glass (SOG) cap to form vacuum encapsulation. To realize a wide range of pressure measurements, silicon islands were deployed on the device layer of the SOI wafer to enhance equivalent stiffness and structural stability of the pressure-sensitive diaphragm. Moreover, a cylindrical vacuum cavity was deployed on the SOG cap with the purpose to decrease the stresses generated during the silicon-to-glass contact during pressure measurements. The fabrication processes mainly contained photolithography, deep reactive ion etching (DRIE), chemical mechanical planarization (CMP) and anodic bonding. According to the characterization experiments, the quality factors of the resonators were higher than 15,000 with pressure sensitivities of 0.51 Hz/kPa (resonator I), −1.75 Hz/kPa (resonator II) and temperature coefficients of frequency of 1.92 Hz/°C (resonator I), 1.98 Hz/°C (resonator II). Following temperature compensation, the fitting error of the microsensor was within the range of 0.006% FS and the measurement accuracy was as high as 0.017% FS in the pressure range of 200 ~ 7000 kPa and the temperature range of −40 °C to 80 °C.

Wafer-Scale Integration for Semi-Flexible Neural Implant Miniaturization

We present a novel, wafer-based fabrication process that enables integration and assembly of electronic components, such as ASICs and decoupling capacitors, with flexible interconnects. The electronic components are fabricated in, or placed on precisely defined and closely-spaced silicon islands that are connected by interconnects embedded in parylene-based flexible thin film. This fully CMOS compatible approach uses optimized DRIE processes and an SiO2 mesh-shaped mask, allowing for the simultaneous definition of micrometer- to millimeter-sized structures without compromising the flexibility of the device. In a single fabrication flow a unique freedom in dimensions of both the flexible film and the silicon islands can be achieved making this new technique ideal for the realization of semi-flexible/foldable implantable devices, where structures of different sizes have to be combined together for the ultimate miniaturization.