Fabrication of SOI MOSFET by Separation by Bonding Silicon Islands (SBSI) Method

2019 ◽  
Vol 6 (4) ◽  
pp. 309-313 ◽  
Author(s):  
Kei Kanemoto ◽  
Hideaki Oka ◽  
Hirokazu Hisamatsu ◽  
Yusuke Matsuzawa ◽  
Yoji Kitano ◽  
...  
Keyword(s):  
Soi Mosfet ◽  
Silicon Islands

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals A Resonant Pressure Microsensor with a Wide Pressure Measurement Range

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 382
Author(s):  
Chao Xiang ◽  
Yulan Lu ◽  
Chao Cheng ◽  
Junbo Wang ◽  
Deyong Chen ◽  
...  
Keyword(s):  
Chemical Mechanical Planarization ◽  
Measurement Range ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Pressure Measurements ◽  
Quality Factors ◽  
Deep Reactive Ion Etching ◽  
Wide Range ◽  
Form Pressure ◽  
Silicon Islands

This paper presents a resonant pressure microsensor with a wide range of pressure measurements. The developed microsensor is mainly composed of a silicon-on-insulator (SOI) wafer to form pressure-sensing elements, and a silicon-on-glass (SOG) cap to form vacuum encapsulation. To realize a wide range of pressure measurements, silicon islands were deployed on the device layer of the SOI wafer to enhance equivalent stiffness and structural stability of the pressure-sensitive diaphragm. Moreover, a cylindrical vacuum cavity was deployed on the SOG cap with the purpose to decrease the stresses generated during the silicon-to-glass contact during pressure measurements. The fabrication processes mainly contained photolithography, deep reactive ion etching (DRIE), chemical mechanical planarization (CMP) and anodic bonding. According to the characterization experiments, the quality factors of the resonators were higher than 15,000 with pressure sensitivities of 0.51 Hz/kPa (resonator I), −1.75 Hz/kPa (resonator II) and temperature coefficients of frequency of 1.92 Hz/°C (resonator I), 1.98 Hz/°C (resonator II). Following temperature compensation, the fitting error of the microsensor was within the range of 0.006% FS and the measurement accuracy was as high as 0.017% FS in the pressure range of 200 ~ 7000 kPa and the temperature range of −40 °C to 80 °C.

scholarly journals Cavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 414
Author(s):  
Marta Maria Kluba ◽  
Jian Li ◽  
Katja Parkkinen ◽  
Marcus Louwerse ◽  
Jaap Snijder ◽  
...  
Keyword(s):  
Complex Geometry ◽  
Pressure Sensors ◽  
Silicon On Insulator ◽  
Test Case ◽  
Mems Devices ◽  
Device Layer ◽  
Mems Fabrication ◽  
Silicon Islands ◽  
Design Freedom ◽  
Deep Brain

Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

Controlling of Floating-Body and Thermal Conductivity in Short Channel SOI MOSFET at 30 nm Channel Node

Silicon ◽  
2021 ◽  
Author(s):  
Pradipta Dutta ◽  
SubhashreeSoubhagyamayee Behera ◽  
Soumendra Prasad Rout
Keyword(s):  
Thermal Conductivity ◽  
Floating Body ◽  
Short Channel ◽  
Soi Mosfet

Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region

2008 ◽  
Vol 55 (3) ◽  
pp. 789-795 ◽  
Author(s):  
Pradeep Agarwal ◽  
Govind Saraswat ◽  
M. Jagadesh Kumar
Keyword(s):  
Surface Potential ◽  
Potential Model ◽  
Depletion Region ◽  
Compact Surface ◽  
Soi Mosfet

Proposal of preliminary device model and scaling scheme of cross-current tetrode SOI MOSFET aiming at low-energy circuit applications

2011 ◽  
Vol 64 (1) ◽  
pp. 18-27 ◽  
Author(s):  
Yasuhisa Omura ◽  
Azuma Yu ◽  
Yoshimasa Yoshioka ◽  
Kyota Fukuchi ◽  
Daishi Ino
Keyword(s):  
Low Energy ◽  
Soi Mosfet ◽  
Device Model ◽  
Cross Current
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