scholarly journals A Resonant Pressure Microsensor with a Wide Pressure Measurement Range

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 382
Author(s):  
Chao Xiang ◽  
Yulan Lu ◽  
Chao Cheng ◽  
Junbo Wang ◽  
Deyong Chen ◽  
...  
Keyword(s):  
Chemical Mechanical Planarization ◽  
Measurement Range ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Pressure Measurements ◽  
Quality Factors ◽  
Deep Reactive Ion Etching ◽  
Wide Range ◽  
Form Pressure ◽  
Silicon Islands

This paper presents a resonant pressure microsensor with a wide range of pressure measurements. The developed microsensor is mainly composed of a silicon-on-insulator (SOI) wafer to form pressure-sensing elements, and a silicon-on-glass (SOG) cap to form vacuum encapsulation. To realize a wide range of pressure measurements, silicon islands were deployed on the device layer of the SOI wafer to enhance equivalent stiffness and structural stability of the pressure-sensitive diaphragm. Moreover, a cylindrical vacuum cavity was deployed on the SOG cap with the purpose to decrease the stresses generated during the silicon-to-glass contact during pressure measurements. The fabrication processes mainly contained photolithography, deep reactive ion etching (DRIE), chemical mechanical planarization (CMP) and anodic bonding. According to the characterization experiments, the quality factors of the resonators were higher than 15,000 with pressure sensitivities of 0.51 Hz/kPa (resonator I), −1.75 Hz/kPa (resonator II) and temperature coefficients of frequency of 1.92 Hz/°C (resonator I), 1.98 Hz/°C (resonator II). Following temperature compensation, the fitting error of the microsensor was within the range of 0.006% FS and the measurement accuracy was as high as 0.017% FS in the pressure range of 200 ~ 7000 kPa and the temperature range of −40 °C to 80 °C.

scholarly journals Using the Nonlinear Duffing Effect of Piezoelectric Micro-Oscillators for Wide-Range Pressure Sensing

Actuators ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 172
Author(s):  
Tobias Zengerle ◽  
Michael Stopp ◽  
Abdallah Ababneh ◽  
Helmut Seidel
Keyword(s):  
Duffing Oscillator ◽  
Cost Effective ◽  
Measurement Range ◽  
Theoretical Background ◽  
Pressure Measurements ◽  
Softening Effect ◽  
Coverage Area ◽  
Novel Approach ◽  
Wide Range ◽  
Bending Modes

This paper investigates the resonant behaviour of silicon-based micro-oscillators with a length of 3600 µm, a width of 1800 µm and a thickness of 10 µm over a wide range of ambient gas (N2) pressures, extending over six orders of magnitude from 10−3 mbar to 900 mbar. The oscillators are actuated piezoelectrically by a thin-film aluminium-nitride (AlN) layer, with the cantilever coverage area being varied from 33% up to 100%. The central focus is on nonlinear Duffing effects, occurring at higher oscillation amplitudes. A theoretical background is provided. All relevant parameters describing a Duffing oscillator, such as stiffness parameters for each coverage size as well as for different bending modes and more complex modes, are extracted from the experimental data. The so-called 2nd roof-tile-shaped mode showed the highest stiffness value of −97.3∙107 m−2s−2. Thus, it was chosen as being optimal for extended range pressure measurements. Interestingly, both a spring softening effect and a spring hardening effect were observed in this mode, depending on the percentage of the AlN coverage area. The Duffing-effect-induced frequency shift was found to be optimal for obtaining the highest pressure sensitivity, while the size of the hysteresis loop is also a very useful parameter because of the possibility of eliminating the temperature influences and long-term drift effects of the resonance frequency. An reasonable application-specific compromise between the sensitivity and the measurement range can be selected by adjusting the excitation voltage, offering much flexibility. This novel approach turns out to be very promising for compact, cost-effective, wide-range pressure measurements in the vacuum range.

scholarly journals Photonic Crystal Nanobeam Cavities for Nanoscale Optical Sensing: A Review

Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 72 ◽  
Author(s):  
Da-Quan Yang ◽  
Bing Duan ◽  
Xiao Liu ◽  
Ai-Qiang Wang ◽  
Xiao-Gang Li ◽  
...  
Keyword(s):  
Photonic Crystal ◽  
Optical Waveguides ◽  
Optical Sensing ◽  
Early Stage ◽  
Disease Diagnosis ◽  
Label Free ◽  
Quality Factors ◽  
Integrated Sensor ◽  
Early Stage Disease ◽  
Wide Range

The ability to detect nanoscale objects is particular crucial for a wide range of applications, such as environmental protection, early-stage disease diagnosis and drug discovery. Photonic crystal nanobeam cavity (PCNC) sensors have attracted great attention due to high-quality factors and small-mode volumes (Q/V) and good on-chip integrability with optical waveguides/circuits. In this review, we focus on nanoscale optical sensing based on PCNC sensors, including ultrahigh figure of merit (FOM) sensing, single nanoparticle trapping, label-free molecule detection and an integrated sensor array for multiplexed sensing. We believe that the PCNC sensors featuring ultracompact footprint, high monolithic integration capability, fast response and ultrahigh sensitivity sensing ability, etc., will provide a promising platform for further developing lab-on-a-chip devices for biosensing and other functionalities.

scholarly journals Cavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 414
Author(s):  
Marta Maria Kluba ◽  
Jian Li ◽  
Katja Parkkinen ◽  
Marcus Louwerse ◽  
Jaap Snijder ◽  
...  
Keyword(s):  
Complex Geometry ◽  
Pressure Sensors ◽  
Silicon On Insulator ◽  
Test Case ◽  
Mems Devices ◽  
Device Layer ◽  
Mems Fabrication ◽  
Silicon Islands ◽  
Design Freedom ◽  
Deep Brain

Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

scholarly journals Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Ultrasonic Transducer ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Lateral Side ◽  
Membrane Thickness ◽  
Bonding Performance ◽  
Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

SILICON FIBRE TECHNOLOGY DEVELOPMENT FOR WEARABLE AND AMBIENT ELECTRONICS APPLICATIONS

2006 ◽  
Vol 16 (02) ◽  
pp. 713-721
Author(s):  
THOMAS HEALY ◽  
JULIE DONNELLY ◽  
BRENDAN O'NEILL ◽  
JOHN ALDERMAN ◽  
ALAN MATHEWSON
Keyword(s):  
Technology Development ◽  
Silicon On Insulator ◽  
Monitoring Systems ◽  
Active Device ◽  
Fibre Technology ◽  
Wide Range ◽  
Silicon Structures ◽  
Health Monitoring Systems ◽  
Anisotropic Etch ◽  
Ic Technology

The concept of silicon fibre technology follows the aspiration of making whole computers recede into textile format, which can be used in a wearable or ambient environment. The integration of IC technology into fibre format is an important development for a wide range of emerging scientific applications from wearable vital sign health monitoring systems [1] to Ambient Intelligence Microsystems. This concept is achieved by building a device in silicon on insulator (SOI) [2] material and under-cutting the sacrificial SiO 2 layer by a combination of isotropic and anisotropic etch processes, to leave a freestanding functional fibre. A demonstration of functionality based on this technology was produced in the form of a PN diode on a fibre [3]. After demonstrating the feasibility of the concept, subsequent active device circuits were designed and fabricated as a more complex demonstration of functionality. One of the primary considerations involved with this technology is the interconnection of these flexible silicon structures to each other and to the outside environment. A novel interconnection protocol has been developed and a prototype demonstration of a flexible LED circuit has been fabricated.

Finite Element Modelling of Air-Coupled Circular Capacitive Micromachined Ultrasonic Transducer for Anodic Bonding Process using SOI Wafer

2021 ◽  
Author(s):  
Gurpreet Singh Gill ◽  
Sanjay Kumar ◽  
Ravindra Mukhiya ◽  
Vinod Kumar Khanna
Keyword(s):  
Finite Element ◽  
Resonance Frequency ◽  
Glass Substrate ◽  
Ultrasonic Transducer ◽  
Fem Simulation ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Free Standing ◽  
Design Flexibility ◽  
Capacitive Micromachined Ultrasonic Transducer

Abstract Capacitive Micromachined Ultrasonic Transducer (CMUT) provides an alternative to commercial piezoelectric-based ultrasonic transducers due to its wide bandwidth, improved efficiency, sensitivity, and design flexibility [1, 2]. In this paper, Finite Element Method-based design and simulations of circular capacitive micromachined ultrasonic transducer (CMUT) is presented. The FEM simulation of air-coupled CMUT was accomplished by using MEMCAD tools CoventorWare® and COMSOL™. The resonance frequency of 3.9 MHz was achieved for the designed circular CMUT device. A favourable agreement was found for the resonance frequency and pull-in voltage of the device using MEMSCAD tools and analytical calculations. For the proposed CMUT design, a circular cavity will be formed inside the glass substrate. Then, a free-standing membrane will be released using active layer of silicon-on-insulator (SOI) wafer. The bulk silicon of SOI wafer will be removed after bonding it on the glass substrate using anodic bonding technique as described in fabrication process flow for CMUT.

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