Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

2018 ◽  
Vol 15 (4) ◽  
pp. 163-170 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Combustion Engine ◽  
Circuit Complexity ◽  
Fold Increase ◽  
Ring Oscillator ◽  
Well Drilling ◽  
Deep Well ◽  
Air Atmosphere ◽  
And Control

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000071-000078 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Combustion Engine ◽  
Circuit Complexity ◽  
Fold Increase ◽  
Ring Oscillator ◽  
Well Drilling ◽  
Deep Well ◽  
Air Atmosphere ◽  
One Year

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 °C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Processing and Characterization of Thousand-Hour 500 °C Durable 4H-SiC JFET Integrated Circuits

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000249-000256 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Liang-Yu Chen ◽  
Dorothy Lukco ◽  
Carl W. Chang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Ohmic Contacts ◽  
Combustion Engine ◽  
Well Drilling ◽  
Deep Well ◽  
Operational Testing ◽  
And Control ◽  
Technology Foundation

Abstract This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 °C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over ~ 1-μm scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 °C operational testing. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

Design and Calibration of Resistive Stress Sensors on 4H Silicon Carbide

2018 ◽  
Author(s):  
Richard C. Jaeger ◽  
Jun Chen ◽  
Jeffrey C. Suhling ◽  
Leonid Fursin
Keyword(s):  
Silicon Carbide ◽  
Integrated Circuits ◽  
Stress Sensitivity ◽  
Well Drilling ◽  
Deep Well ◽  
Stress Sensors ◽  
Wide Range ◽  
Higher Temperature ◽  
Van Der Pauw ◽  
Transverse Piezoresistance

Stress sensors have shown potential to provide “health monitoring” of a wide range of issues related to packaging of integrated circuits, and silicon carbide offers the advantage of much higher temperature sensor operation with application in packaged high-voltage, high-power SiC devices as well as both automotive and aerospace systems, geothermal plants, and deep well drilling, to name a few. This paper discusses the theory and uniaxial calibration of resistive stress sensors on 4H silicon carbide (4H-SiC) and provides new theoretical descriptions for four-element resistor rosettes and van der Pauw (VDP) stress sensors. The results delineate the similarities and differences relative to those on (100) silicon: resistors on the silicon face of 4H-SiC respond to only four of the six components of the stress state; a four-element rosette design exists for measuring the in-plane stress components; two stress quantities can be measured in a temperature compensated manner. In contrast to silicon, only one combined coefficient is required for temperature compensated stress measurements. Calibration results from a single VDP device can be used to calculate the basic lateral and transverse piezoresistance coefficients for 4H-SiC material. Experimental results are presented for lateral and transverse piezoresistive coefficients for van der Pauw structures and p- and n-type resistors. The VDP devices exhibit the expected 3.16 times higher stress sensitivity than standard resistor rosettes.

scholarly journals Hybrid Obfuscation with key Based Encryption for Integrated Circuits

2019 ◽  
Vol 9 (2) ◽  
pp. 3215-3220
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Design Space ◽  
Functional Encryption ◽  
Control Overhead ◽  
Secret Keys ◽  
Key Length ◽  
Encryption Method ◽  
And Control ◽  
Encryption Function

A new functional encryption method applied for integrated circuit (IC) is proposed in this paper which is called as hybrid obfuscation. The hardware obfuscation or encryption function is a countermeasures act utilized to provide safety of circuit from malware attack and unauthorized entry at the time of manufacture by the distrusted foundries across the world. The purpose of encryption is to design and embed secret keys for achieving functional modifications at the design space itself. Such keys are programmed suddenly inside the ICs when they are obtained from the factory. Since the distrusted factory doesn't approach the key, they can't dispose of the extra components of the chip which doesn't work effectively without the key. By joining existing procedures of obscurity known as fixed obfuscation and dynamic obfuscation, the half and half muddling strategy accomplish the objectives of an encryption function. The investigation of safety efforts proves that the functional encryption enhances the design security as contrasted with existing method. In addition, the proposed method decreases zone overhead by 40% and control overhead by 30% for a key length of 30 bits contrasted with the active obscurity

Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors

1996 ◽  
Vol 8 (6) ◽  
pp. 508-515 ◽  
Author(s):  
Tadashi Shibata ◽  
◽  
Tadahiro Ohmi
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Intelligent Systems ◽  
Circuit Complexity ◽  
Primary Objective ◽  
Electronic Circuits ◽  
Circuit Element ◽  
Hardware Configuration ◽  
Input Gate ◽  
Intelligent Data Processing

The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due to its functional similarity to a simple neuron model. vMOS circuits are characterized by a high degree of parallelism in hardware computation, large flexibility in the hardware configuration, and a dramatic reduction in circuit complexity compared to conventional integrated circuits. As a result, a number of new-concept circuits has been developed. Examples include a real-time reconfigurable logic circuit called flexware and associative memory conducting a fully parallel search for the most similar targets. A simple hardware model for self-learning systems is also presented. The enhancement in functionality at a very elemental transistor level is critical to building human-like intelligent systems on silicon.

scholarly journals Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor

2018 ◽  
Vol 8 (8) ◽  
pp. 1331 ◽  
Author(s):  
Yasunori Takeda ◽  
Tomohito Sekine ◽  
Rei Shiwaku ◽  
Tomohide Murase ◽  
Hiroyuki Matsui ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Ring Oscillator ◽  
Driving Voltage ◽  
Organic Thin Film ◽  
Voltage Range ◽  
Type D ◽  
Polymer Semiconductor ◽  
P Type

The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 °C

2008 ◽  
Vol 1069 ◽  
Author(s):  
Philip Neudeck ◽  
David J. Spry ◽  
Liang-Yu Chen ◽  
Carl W. Chang ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect Transistors ◽  
Aircraft Engines ◽  
Electrical Parameters ◽  
Air Atmosphere ◽  
Circuit Technology ◽  
Very High

ABSTRACTNASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 °C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 °C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

scholarly journals Application of TIVA in Design Debug

2000 ◽  
Author(s):  
Siva Kolachina ◽  
Bill Taylor ◽  
Kendall Scott Wills ◽  
Edward I. Cole
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Ring Oscillator ◽  
Induced Voltage ◽  
Thermally Induced ◽  
Isolation Techniques ◽  
Limited Success ◽  
Focussed Ion Beam ◽  
Design Debugging

Abstract Thermally-Induced Voltage Alteration (TIVA) is a relatively new technique for locating electrical defects in integrated circuits [1,2]. This paper describes a novel application of TIVA, to locate design anomalies. A newly designed integrated circuit with high and inconsistent Quiescent Power Supply Current (IDDQ) was initially diagnosed with limited success using various failsite isolation techniques. The TIVA technique was successful in accurately locating design anomalies. Results from TIVA identified a spurious ring oscillator in the design. Design modifications carried out using a focussed ion beam (FIB), verified the accuracy of the results from TIVA. This study clearly extends the use of TIVA beyond that of locating electrical defects and anomalies into the realm of design debugging.

A Simple Method of Transistor-Level SPICE-Models Parameters Fitting of Integrated Circuits in a Temperature Range

2021 ◽  
Vol 26 (6) ◽  
pp. 547-553
Author(s):  
S.V. Shumarin ◽  
◽  
A.M. Bogachev ◽  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Fitting ◽  
Circuit Model ◽  
The Self ◽  
Ring Oscillator ◽  
Simple Method ◽  
Correlation Relationship ◽  
Temperature Range ◽  
Before And After

Today, both macromodels and transistor-level models of semiconductor integrated circuits are available. However, most models don’t take into account the influence of destabilizing effects. Thus, the tasks of developing new models and fitting the parameters of existing ones are very relevant. In this work, the authors introduced an assumption about the existence of a correlation relationship between all the parameters of integrated circuits’ transistor-level models and offered a way to fit these parameters. The experience of fitting the model’s parameters of the integrated circuit 1564LE1 EP was presented. To simplify this task, all parameters were altered by the same relative deviation. To check the assumption made, the authors carried out full-scale experiment, in which the frequency of the self-oscillation of the ring oscillator based on the 1564LE1 EP was measured in the temperature range. The simulation of the ring oscillator has been made using a SPICE-simulator. The dependences of the self-oscillation frequency on temperature, obtained as a result of simulation and as a result of experiment, were compared before and after fitting the parameters of the integrated circuit model. Also, the waveforms of the ring oscillator based on the original and fitted model were compared. The analysis of the obtained dependences of the frequency of oscillations, the signal shape before and after the model fitting, the link to the text of the fitted model has been provided. The results obtained show the possibility of using the introduced assumption to fit the parameters of the transistor-level integrated circuit model.

Laser-Chemical Deposition and Etching on the Metallization Level of Integrated Circuits

1986 ◽  
Vol 75 ◽  
Author(s):  
A. Wayne Johnson ◽  
K. E. Greenberg
Keyword(s):  
Integrated Circuits ◽  
Circuit Design ◽  
Integrated Circuit ◽  
Pulsed Laser ◽  
Chemical Deposition ◽  
Chemical Vapor ◽  
Laser Chemical Vapor Deposition ◽  
Chlorine Gas ◽  
Doped Silicon ◽  
And Control

AbstractLaser-controlled chemical deposition and etching techniques were used to modify integrated circuits. This work used a pulsed laser to initiate and control the etching, by chlorine gas, of aluminum conductors. New conducting paths were then formed by laser-chemical vapor deposition of highly-doped silicon from silane and diborane. Improved conductivity of laser-deposited connectors was achieved by the selective deposition of tungsten on the silicon. These techniques were used to “rewire” an integrated circuit allowing the full evaluation of the corrected circuit design.

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