scholarly journals Printed Organic Complementary Inverter with Single SAM Process Using a p-type D-A Polymer Semiconductor

2018 ◽  
Vol 8 (8) ◽  
pp. 1331 ◽  
Author(s):  
Yasunori Takeda ◽  
Tomohito Sekine ◽  
Rei Shiwaku ◽  
Tomohide Murase ◽  
Hiroyuki Matsui ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Ring Oscillator ◽  
Driving Voltage ◽  
Organic Thin Film ◽  
Voltage Range ◽  
Type D ◽  
Polymer Semiconductor ◽  
P Type

The demonstration of the complementary integrated circuit using printing processes is indispensable for realizing electronic devices using organic thin film transistors. Although complementary integrated circuits have advantages such as low power consumption and a wide output voltage range, complementary integrated circuits fabricated by the printing method have problems regarding driving voltage and performance. Studies on fabrication processes of electronic circuits for printing technology, including optimization and simplification, are also important research topics. In this study, the fabrication process of the printed complementary integrated circuit was simplified by applying a p-type donor-acceptor (D-A) polymer semiconductor, which is not strongly affected by the electrode work function. An inverter circuit and the ring oscillator circuit were demonstrated using this process. The fabricated ring oscillator array showed excellent performance, with low voltage operation and low performance variation.

High-Performance Low Voltage Organic Thin-Film Transistors

2005 ◽  
Vol 870 ◽  
Author(s):  
Stijn De Vusser ◽  
Soeren Steudel ◽  
Kris Myny ◽  
Jan Genoe ◽  
Paul Heremans
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Organic Thin Film Transistors ◽  
Ring Oscillator ◽  
Ring Oscillators ◽  
Organic Thin Film ◽  
Supply Voltages

AbstractIn this work, we report on high-performance low voltage pentacene Organic Thin-Film Transistors (OTFT's) and circuits. Inverters and ring oscillators have been designed and fabricated. At 15 V supply voltage, we have observed invertors showing a voltage gain of 9 and an output swing of more than 13 V. As for the ring oscillators, oscillations started at supply voltages as low as 8.5 V. At a supply voltage of only 15 V, a stage delay time of 3.3 νs is calculated from experimental results.We believe that these results show for the first time a high speed ring oscillator at relatively low supply voltages. The required supply voltages can be obtained by rectification using an organic (pentacene) diode. These results may have an important impact on the realization of RF-ID tags: by integrating our circuits with an organic diode, the fabrication of organic RF-ID tags comes closer.

An Organic, Threshold Voltage Based, All PMOS, Voltage Reference Generator for Flexible Sensor Tags

2021 ◽  
Author(s):  
Mohammad Azimi ◽  
Mehdi Habibi ◽  
Hamid Reza Karimi-Alavijeh
Keyword(s):  
Integrated Circuits ◽  
Organic Semiconductors ◽  
Threshold Voltage ◽  
Integrated Circuit ◽  
Work Performance ◽  
Voltage Reference ◽  
Electronic Circuits ◽  
Performance Factors ◽  
Reference Generator ◽  
P Type

Abstract The developments and advances achieved in organic semiconductors have promised lower costs for integrated circuit productions and also the fabrication of electronic circuits using printed technology on unconventional substrates such as plastic, clothing, and even skin. An important building block essential to most electronic circuits is a voltage, process, and temperature independent potential generator which can be used to bias amplifiers and produce a fixed reference for sensor devices. The generation of a voltage reference is also important for voltage regulators. Currently, most reported organic integrated circuits use only p-type OFETs in their circuits due to simpler fabrication procedures. Furthermore, air stable p-type organic semiconductors such as Pentacene and CuPc are well characterized. In this paper, a low power two stage all PMOS voltage reference generator is proposed. As properties such as threshold voltage value and device aging are dependent on the OFET structure, the type of device chosen for this purpose will have a direct impact on the circuit performance. Three different types of OFETs with silver, copper, and gold drain/source electrodes are studied in this work. Performance factors such as Line Sensitivity (LS), Temperature Coefficient (TC), power consumption, time constant, and output drifts of the fabricated integrated circuits are measured and reported to verify the characteristics of the proposed circuit. It is shown that the drain/source metal choice affects the threshold voltage dependent output potential of the reference generators.

scholarly journals Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

2020 ◽  
Vol 15 (1) ◽  
Author(s):  
Ruibo Chen ◽  
Hongxia Liu ◽  
Wenqiang Song ◽  
Feibo Du ◽  
Hao Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Triggering Mechanism ◽  
Esd Protection ◽  
Tcad Simulation ◽  
P Type ◽  
28 Nm ◽  
Latch Up

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

Year-long 500°C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

2018 ◽  
Vol 15 (4) ◽  
pp. 163-170 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Combustion Engine ◽  
Circuit Complexity ◽  
Fold Increase ◽  
Ring Oscillator ◽  
Well Drilling ◽  
Deep Well ◽  
Air Atmosphere ◽  
And Control

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

scholarly journals Digital On-Chip Calibration of Analog Systems towards Enhanced Reliability

2021 ◽  
Author(s):  
Michal Sovcik ◽  
Lukas Nagy ◽  
Viera Stopjakova ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic System ◽  
Digital Calibration ◽  
Electrical Stress ◽  
Offset Voltage ◽  
On Chip ◽  
Analog Systems

This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600 mV with 10% variation, in temperature range from − 20 ° C to 85 ° C . Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13 μV to 167 μV . With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA.

Silicon-on-lnsulator Technology: Past Achievements and Future Prospects

MRS Bulletin ◽  
1998 ◽  
Vol 23 (12) ◽  
pp. 16-19 ◽  
Author(s):  
Jean-Pierre Colinge
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Current Gain ◽  
Silicon Devices ◽  
Microelectronics Industry ◽  
Radiation Hard ◽  
Soi Technology

In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.

Modeling of two complementary ambipolar organic thin film Transistors. Application to organic inverter

2020 ◽  
Author(s):  
Houaida Becharguia ◽  
M. Mahdouani ◽  
R. Bourguiga
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
Organic Semiconductors ◽  
Thin Film Transistors ◽  
Organic Thin Film Transistors ◽  
Organic Transistors ◽  
Organic Thin Film ◽  
Electrical Parameters ◽  
P Type ◽  
Organic Inverter

In this paper, we have study two types of thin-film organic transistors as well as the organic inverter. For manufacturing p-type and n-type organic thin film transistors (OTFT), pentacene and N,N’-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (PTCDI-C13H27) were used as organic semiconductors. The organic thin film transistors showed excellent ambipolar operation. This ambipolar device is very useful in building flexible integrated circuits with easy design and low power consumption. The characterization and modeling of complementary thin film organic transistors allows us to describe one of its important applications which are the "inverter". In order to better understand the operation of inverters, an analytical model has been developed to describe the electrical behavior of both types of transistors and organic inverter. The model was carried out for transistors and organic inverters made experimentally. In this present work, we present the different electrical parameters resulting from the modeling for the two types of transistors and the organic inverter wich based on the complementary OTFTs.

Yearlong 500 °C Operational Demonstration of Up-scaled 4H-SiC JFET Integrated Circuits

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000071-000078 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Combustion Engine ◽  
Circuit Complexity ◽  
Fold Increase ◽  
Ring Oscillator ◽  
Well Drilling ◽  
Deep Well ◽  
Air Atmosphere ◽  
One Year

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 °C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 °C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 °C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016 [1]. These results advance the technology foundation for realizing long-term durable 500 °C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

scholarly journals Application of TIVA in Design Debug

2000 ◽  
Author(s):  
Siva Kolachina ◽  
Bill Taylor ◽  
Kendall Scott Wills ◽  
Edward I. Cole
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Ion Beam ◽  
Ring Oscillator ◽  
Induced Voltage ◽  
Thermally Induced ◽  
Isolation Techniques ◽  
Limited Success ◽  
Focussed Ion Beam ◽  
Design Debugging

Abstract Thermally-Induced Voltage Alteration (TIVA) is a relatively new technique for locating electrical defects in integrated circuits [1,2]. This paper describes a novel application of TIVA, to locate design anomalies. A newly designed integrated circuit with high and inconsistent Quiescent Power Supply Current (IDDQ) was initially diagnosed with limited success using various failsite isolation techniques. The TIVA technique was successful in accurately locating design anomalies. Results from TIVA identified a spurious ring oscillator in the design. Design modifications carried out using a focussed ion beam (FIB), verified the accuracy of the results from TIVA. This study clearly extends the use of TIVA beyond that of locating electrical defects and anomalies into the realm of design debugging.

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