Laser-Chemical Deposition and Etching on the Metallization Level of Integrated Circuits

1986 ◽  
Vol 75 ◽  
Author(s):  
A. Wayne Johnson ◽  
K. E. Greenberg

AbstractLaser-controlled chemical deposition and etching techniques were used to modify integrated circuits. This work used a pulsed laser to initiate and control the etching, by chlorine gas, of aluminum conductors. New conducting paths were then formed by laser-chemical vapor deposition of highly-doped silicon from silane and diborane. Improved conductivity of laser-deposited connectors was achieved by the selective deposition of tungsten on the silicon. These techniques were used to “rewire” an integrated circuit allowing the full evaluation of the corrected circuit design.

2008 ◽  
Vol 18 (04) ◽  
pp. 901-910
Author(s):  
RAGNAR KIEBACH ◽  
ZHENRUI YU ◽  
MARIANO ACEVES-MIJARES ◽  
DONGCAI BIAN ◽  
JINHUI DU

The formation of nano sized Si structures during the annealing of silicon rich oxide (SRO) films was investigated. These films were synthesized by low pressure chemical vapor deposition (LPCVD) and used as precursors, a post-deposition thermal annealing leads to the formation of Si nano crystals in the SiO 2 matrix and Si nano islands ( Si nI ) at c-Si /SRO interface. The influences of the excess Si concentration, the incorporation of N in the SRO precursors, and the presence of a Si concentration gradient on the Si nI formation were studied. Additionally the influence of pre-deposition substrate surface treatments on the island formation was investigated. Therefore, the substrate surface was mechanical scratched, producing high density of net-like scratches on the surface. Scanning electron microscopy (SEM) and high resolution transmission electron microscopy (HRTEM) were used to characterize the synthesized nano islands. Results show that above mentioned parameters have significant influences on the Si nIs . High density nanosized Si islands can epitaxially grow from the c-Si substrate. The reported method is very simple and completely compatible with Si integrated circuit technology.


1998 ◽  
Vol 555 ◽  
Author(s):  
Ashok Kumar ◽  
R. Alexandrescu

AbstractWe have investigated the growth of carbon nitride (CNx) coatings on various substrates using laser assisted methods such as pulsed laser deposition (PLD) and laser chemical vapor deposition (LCVD). It has been shown that the both techniques produce good quality thin films of CNx. In PLD, a laser beam (λ= 248 nm) has been used to ablate the pyrolytic graphite target in nitrogen atmosphere, where as CO2 laser was used to irradiate carbon-nitrogen containing mixtures such as C2H2/N20/NH3 in LCVD method. A comparative analysis will be presented in terms of structural properties of CNx films prepared by both techniques.


2006 ◽  
Vol 125 (8) ◽  
pp. 084701 ◽  
Author(s):  
Shojiro Komatsu ◽  
Daisuke Kazami ◽  
Hironori Tanaka ◽  
Yusuke Moriyoshi ◽  
Masaharu Shiratani ◽  
...  

A new functional encryption method applied for integrated circuit (IC) is proposed in this paper which is called as hybrid obfuscation. The hardware obfuscation or encryption function is a countermeasures act utilized to provide safety of circuit from malware attack and unauthorized entry at the time of manufacture by the distrusted foundries across the world. The purpose of encryption is to design and embed secret keys for achieving functional modifications at the design space itself. Such keys are programmed suddenly inside the ICs when they are obtained from the factory. Since the distrusted factory doesn't approach the key, they can't dispose of the extra components of the chip which doesn't work effectively without the key. By joining existing procedures of obscurity known as fixed obfuscation and dynamic obfuscation, the half and half muddling strategy accomplish the objectives of an encryption function. The investigation of safety efforts proves that the functional encryption enhances the design security as contrasted with existing method. In addition, the proposed method decreases zone overhead by 40% and control overhead by 30% for a key length of 30 bits contrasted with the active obscurity


2018 ◽  
Vol 15 (4) ◽  
pp. 163-170 ◽  
Author(s):  
Philip G. Neudeck ◽  
David J. Spry ◽  
Michael J. Krasowski ◽  
Norman F. Prokop ◽  
Glenn M. Beheim ◽  
...  

Abstract This work describes recent progress in the design, processing, and testing of significantly up-scaled complex 500°C–durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for more than 1 y at 500°C in an air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C–durable circuit complexity from the 24-transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500°C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.


1982 ◽  
Vol 19 (3) ◽  
pp. 265-270
Author(s):  
H. E. Hanrahan ◽  
S. J. West

Recent advances in VLSI digital circuit design methods and the silicon foundry concept has put the design of such circuits within reach of students. This paper discusses the design of linear integrated circuits by students. The basic concepts, tools and techniques are reviewed. The areas of common ground and differences between analogue and digital design techniques are highlighted.


2017 ◽  
Vol 626 ◽  
pp. 145-153 ◽  
Author(s):  
Kyunghoon Jeong ◽  
Jiwon Lee ◽  
Injae Byun ◽  
Myung-jun Seong ◽  
Jongsoo Park ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document