Enhancing the Quantum Linear Systems Algorithm Using Richardson Extrapolation

We present a quantum algorithm to solve systems of linear equations of the form Ax = b , where A is a tridiagonal Toeplitz matrix and b results from discretizing an analytic function, with a circuit complexity of O (1/√ε, poly (log κ, log N )), where N denotes the number of equations, ε is the accuracy, and κ the condition number. The repeat-until-success algorithm has to be run O (κ/(1-ε)) times to succeed, leveraging amplitude amplification, and needs to be sampled O (1/ε 2 ) times. Thus, the algorithm achieves an exponential improvement with respect to N over classical methods. In particular, we present efficient oracles for state preparation, Hamiltonian simulation, and a set of observables together with the corresponding error and complexity analyses. As the main result of this work, we show how to use Richardson extrapolation to enhance Hamiltonian simulation, resulting in an implementation of Quantum Phase Estimation (QPE) within the algorithm with 1/√ε circuits that can be run in parallel each with circuit complexity 1/√ ε instead of 1/ε. Furthermore, we analyze necessary conditions for the overall algorithm to achieve an exponential speedup compared to classical methods. Our approach is not limited to the considered setting and can be applied to more general problems where Hamiltonian simulation is approximated via product formulae, although our theoretical results would need to be extended accordingly. All the procedures presented are implemented with Qiskit and tested for small systems using classical simulation as well as using real quantum devices available through the IBM Quantum Experience.

Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

Every new generation of wireless communication standard aims to improve the overall performance and quality of service (QoS), compared to the previous generations. Increased data rates, numbers and capabilities of connected devices, new applications, and higher data volume transfers are some of the key parameters that are of interest. To satisfy these increased requirements, the synergy between wireless technologies and optical transport will dominate the 5G network topologies. This work focuses on a fundamental digital function in an orthogonal frequency-division multiplexing (OFDM) baseband transceiver architecture and aims at improving the throughput and circuit complexity of this function. Specifically, we consider the high-order QAM demodulation and apply approximation techniques to achieve our goals. We adopt approximate computing as a design strategy to exploit the error resiliency of the QAM function and deliver significant gains in terms of critical performance metrics. Particularly, we take into consideration and explore four demodulation algorithms and develop accurate floating- and fixed-point circuits in VHDL. In addition, we further explore the effects of introducing approximate arithmetic components. For our test case, we consider 64-QAM demodulators, and the results suggest that the most promising design provides bit error rates (BER) ranging from 10−1 to 10−4 for SNR 0–14 dB in terms of accuracy. Targeting a Xilinx Zynq Ultrascale+ ZCU106 (XCZU7EV) FPGA device, the approximate circuits achieve up to 98% reduction in LUT utilization, compared to the accurate floating-point model of the same algorithm, and up to a 122% increase in operating frequency. In terms of power consumption, our most efficient circuit configurations consume 0.6–1.1 W when operating at their maximum clock frequency. Our results show that if the objective is to achieve high accuracy in terms of BER, the prevailing solution is the approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency and sustains a throughput of 323 Msamples/s.

Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge. Therefore, the FinFETs is an alternative technology due to its superior attributes of non-leakage power, intra-die variability, low-voltage operation, and lower retention voltage of SRAMs. In this study, our previous work on CMOS two-phase clocking adiabatic physical unclonable function (TPCA-PUF) is evaluated in a FinFET device with a 4-bits PUF circuit complexity. The TPCA-PUF-based shorted-gate (SG) and independent-gate (IG) modes of FinFETs are investigated under various ambient temperatures, process variations, and ±20% of supply voltage variations. To validate the proposed TPCA-PUF circuit, the QUALPFU-based Fin-FETs are compared in terms of cyclical energy dissipation, the security metrics of the uniqueness, the reliability, and the bit-error-rate (BER). The proposed TPCA-PUF is simulated using 45 nm process technology with a supply voltage of 1 V. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are 50.13%, 99.57%, and 0.43%, respectively. In addition, it requires a start-up power of 18.32 nW and consumes energy of 2.3 fJ/bit/cycle at the reference temperature of 27 °C.

Alternative negative weight for simpler hardware implementation of synapse device based neuromorphic system

Lately, there has been a rapid increase in the use of software-based deep learning neural networks (S-DNN) for the analysis of unstructured data consumption. For implementation of the S-DNN, synapse-device-based hardware DNN (H-DNN) has been proposed as an alternative to typical Von-Neumann structural computing systems. In the H-DNN, various numerical values such as the synaptic weight, activation function, and etc., have to be realized through electrical device or circuit. Among them, the synaptic weight that should have both positive and negative numerical values needs to be implemented in a simpler way. Because the synaptic weight has been expressed by conductance value of the synapse device, it always has a positive value. Therefore, typically, a pair of synapse devices is required to realize the negative weight values, which leads to additional hardware resources such as more devices, higher power consumption, larger area, and increased circuit complexity. Herein, we propose an alternative simpler method to realize the negative weight (named weight shifter) and its hardware implementation. To demonstrate the weight shifter, we investigated its theoretical, numerical, and circuit-related aspects, following which the H-DNN circuit was successfully implemented on a printed circuit board.

Complexity from spinning primaries

We define circuits given by unitary representations of Lorentzian conformal field theory in 3 and 4 dimensions. Our circuits start from a spinning primary state, allowing us to generalize formulas for the circuit complexity obtained from circuits starting from scalar primary states. These results are nicely reproduced in terms of the geometry of coadjoint orbits of the conformal group. In contrast to the complexity geometry obtained from scalar primary states, the geometry is more complicated and the existence of conjugate points, signaling the saturation of complexity, remains open.

Generic Hardware Private Circuits

With an increasing number of mobile devices and their high accessibility, protecting the implementation of cryptographic functions in the presence of physical adversaries has become more relevant than ever. Over the last decade, a lion’s share of research in this area has been dedicated to developing countermeasures at an algorithmic level. Here, masking has proven to be a promising approach due to the possibility of formally proving the implementation’s security solely based on its algorithmic description by elegantly modeling the circuit behavior. Theoretically verifying the security of masked circuits becomes more and more challenging with increasing circuit complexity. This motivated the introduction of security notions that enable masking of single gates while still guaranteeing the security when the masked gates are composed. Systematic approaches to generate these masked gates – commonly referred to as gadgets – were restricted to very simple gates like 2-input AND gates. Simply substituting such small gates by a secure gadget usually leads to a large overhead in terms of fresh randomness and additional latency (register stages) being introduced to the design.In this work, we address these problems by presenting a generic framework to construct trivially composable and secure hardware gadgets for arbitrary vectorial Boolean functions, enabling the transformation of much larger sub-circuits into gadgets. In particular, we present a design methodology to generate first-order secure masked gadgets which is well-suited for integration into existing Electronic Design Automation (EDA) tools for automated hardware masking as only the Boolean function expression is required. Furthermore, we practically verify our findings by conducting several case studies and show that our methodology outperforms various other masking schemes in terms of introduced latency or fresh randomness – especially for large circuits.

Circuit complexity in U(1) gauge theory

In this paper, we study circuit complexity for a free vector field of a [Formula: see text] gauge theory in Coulomb gauge, and Gaussian states. We introduce a quantum circuit model with Gaussian states, including reference and target states. Using Nielsen’s geometric approach, the complexity then can be found as the shortest geodesic in the space of states. This geodesic is based on the notion of geodesic distance on the Lie group of Bogoliubov transformations equipped with a right-invariant metric. We use the framework of the covariance matrix to compute circuit complexity between Gaussian states. We apply this framework to the free vector field in general dimensions where we compute the circuit complexity of the ground state of the Hamiltonian.

Holographic and QFT complexity with angular momentum

We study the influence of angular momentum on quantum complexity for CFT states holographically dual to rotating black holes. Using the holographic complexity=action (CA) and complexity=volume (CV) proposals, we study the full time dependence of complexity and the complexity of formation for two dimensional states dual to rotating BTZ. The obtained results and their dependence on angular momentum turn out to be analogous to those of charged states dual to Reissner-Nordström AdS black holes. For CA, our computation carefully accounts for the counterterm in the gravity action, which was not included in previous analysis in the literature. This affects the complexity early time dependence and its effect becomes negligible close to extremality. In the grand canonical ensemble, the CA and CV complexity of formation are linear in the temperature, and diverge with the same structure in the speed of light angular velocity limit. For CA the inclusion of the counterterm is crucial for both effects. We also address the problem of studying holographic complexity for higher dimensional rotating black holes, focusing on the four dimensional Kerr-AdS case. Carefully taking into account all ingredients, we show that the late time limit of the CA growth rate saturates the expected bound, and find the CV complexity of formation of large black holes diverges in the critical angular velocity limit. Our holographic analysis is complemented by the study of circuit complexity in a two dimensional free scalar model for a thermofield double (TFD) state with angular momentum. We show how this can be given a description in terms of non-rotating TFD states introducing mode-by-mode effective temperatures and times. We comment on the similarities and differences of the holographic and QFT complexity results.