An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration

2011 ◽  
Vol 8 (4) ◽  
pp. 140-145 ◽  
Author(s):  
Shyh-Shyuan Sheu ◽  
Zhe-Hui Lin ◽  
Jui-Feng Hung ◽  
John H. Lau ◽  
Peng-Shu Chen ◽  
...  
Keyword(s):  
Measuring Method ◽  
Specific Design ◽  
3D Ic ◽  
Measuring Device ◽  
Component Testing ◽  
Testing Method ◽  
Parasitic Parameters ◽  
Frequency Coupling ◽  
Reducing Costs ◽  
Silicon Vias

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000208-000214
Author(s):  
Shyh-Shyuan Sheu ◽  
Zue-Hua Lin ◽  
Jui-Feng Hung ◽  
John H. Lau ◽  
Peng-Shu Chen ◽  
...  
Keyword(s):  
Measuring Method ◽  
Specific Design ◽  
3D Ic ◽  
Measuring Device ◽  
Component Testing ◽  
Testing Method ◽  
Parasitic Parameters ◽  
Frequency Coupling ◽  
Reducing Costs ◽  
Silicon Vias

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieving the function of monitoring the SiO2 thickness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000001-000007
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Cross Sections ◽  
3D Integration ◽  
Leakage Currents ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

scholarly journals Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 1010 ◽  
Author(s):  
Khaoula Ait Belaid ◽  
Hassan Belahrach ◽  
Hassan Ayad
Keyword(s):  
Integrated Circuit ◽  
Inversion Method ◽  
Ic Design ◽  
3D Ic ◽  
Noise Coupling ◽  
Source Characteristics ◽  
Coupling Noise ◽  
The Time Domain ◽  
Silicon Vias ◽  
Domain Coupling

Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated to study and analyze. Therefore, it seems important to find some methods to investigate them. In this paper, a method is proposed to model and compute the time-domain coupling noise in 3D Integrated Circuit (3D-IC) based on TSVs. It is based on the numerical inversion Laplace transform (NILT) method and the chain matrices. The method is validated using some experimental results and the Pspice and Matlab tools. The results confirm the effectiveness of the proposed technique and the noise is analyzed in several cases. It is found that TSV noise coupling is affected by different factors such as source characteristics, horizontal interconnections, and the type of Inputs and Outputs (I/O) drivers.

RF Modeling of Through Silicon Vias (TSVs) in 3D IC

2010 ◽  
Author(s):  
C. W. Luo ◽  
Y. C. Wu ◽  
J. Y. Wang ◽  
S. S. H. Hsu
Keyword(s):  
3D Ic ◽  
Through Silicon Vias ◽  
Silicon Vias
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