scholarly journals Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 1010 ◽  
Author(s):  
Khaoula Ait Belaid ◽  
Hassan Belahrach ◽  
Hassan Ayad
Keyword(s):  
Integrated Circuit ◽  
Inversion Method ◽  
Ic Design ◽  
3D Ic ◽  
Noise Coupling ◽  
Source Characteristics ◽  
Coupling Noise ◽  
The Time Domain ◽  
Silicon Vias ◽  
Domain Coupling

Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated to study and analyze. Therefore, it seems important to find some methods to investigate them. In this paper, a method is proposed to model and compute the time-domain coupling noise in 3D Integrated Circuit (3D-IC) based on TSVs. It is based on the numerical inversion Laplace transform (NILT) method and the chain matrices. The method is validated using some experimental results and the Pspice and Matlab tools. The results confirm the effectiveness of the proposed technique and the noise is analyzed in several cases. It is found that TSV noise coupling is affected by different factors such as source characteristics, horizontal interconnections, and the type of Inputs and Outputs (I/O) drivers.

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application

2012 ◽  
Vol 2012 (1) ◽  
pp. 001038-001045 ◽  
Author(s):  
Sheng-Tsai Wu ◽  
John H. Lau ◽  
Heng-Chieh Chien ◽  
Yu-Lin Chao ◽  
Ra-Min Tain ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Creep Strain ◽  
High Power ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Random Access ◽  
Circuit Board ◽  
3D Ic ◽  
Silicon Vias

In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.

A Micro-channel Cooling Model For a Three-dimensional Integrated Circuit Considering Through-silicon Vias

2020 ◽  
Vol 12 ◽  
Author(s):  
Kang-Jia Wang ◽  
Hong-Chang Sun ◽  
Kui-Zhi Wang
Keyword(s):  
Integrated Circuit ◽  
Heat Dissipation ◽  
Three Dimensional ◽  
Micro Channel ◽  
3D Ic ◽  
Through Silicon Vias ◽  
3D Ics ◽  
Three Dimensional Integrated Circuit ◽  
Silicon Vias ◽  
Cooling Model

Background: With the increase of the integration degree of the three-dimensional integrated circuit(3D IC), the thermal power consumption per unit volume increases greatly, which makes the chip temperature rise. High temperature could affect the performance of the devices and even lead to thermal failure. So, the thermal management for 3D ICs is becoming a major concern. Objective: The aim of the research is to establish a micro-channel cooling model for a three-dimensional integrated circuit(3D IC) considering the through-silicon vias(TSVs). Methods: By studying the structure of the TSVs, the equivalent thermal resistance of each layer is formulated. Then the one-dimensional micro-channel cooling thermal analytical model considering the TSVs was proposed and solved by the existing sparse solvers such as KLU. Results: The results obtained in this paper reveal that the TSVs can effectively improve the heat dissipation, and its maximal temperature reduction is about 10.75%. The theoretical analysis is helpful to optimize the micro-channel cooling system for 3D ICs. Conclusion: The TSV has an important influence on the heat dissipation of 3D IC, which can improve its heat dissipation characteristic

Application of Fast Laser Deprocessing Techniques in Physical Failure Analysis on SRAM Memory of Advance Technology

2014 ◽  
Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Cost Effective ◽  
Tetraethyl Orthosilicate ◽  
Ic Design ◽  
Advance Technology ◽  
Defect Identification ◽  
Technology Scaling ◽  
And Function ◽  
Metal Layers

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

Performance Analysis of Interconnects Based on Carbon Nanotubes for AMS/RF IC Design

2015 ◽  
pp. 336-363 ◽  
Author(s):  
Rafael Vargas-Bernal
Keyword(s):  
Carbon Nanotubes ◽  
Performance Analysis ◽  
Integrated Circuit ◽  
High Speed ◽  
Electrical Current ◽  
Essential Elements ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
Ic Design ◽  
Rf Ic

Electrical interconnects are essential elements to transmit electrical current and/or to apply electrical voltage to the electronic devices found in an integrated circuit. With the introduction of carbon nanotubes in electronic applications, efficient and high-speed interconnects have allowed for optimizing the electrical performance of the integrated circuits. Additionally, technical problems, such as electromigration, large values of parasitic elements, large delays, and high thermal dissipation, presented in metallic interconnects based on copper, can be avoided. This chapter presents a performance analysis of interconnects used in AMS/RF IC design based on carbon nanotubes as the physical material where electrical variables are provided.

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000001-000007
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Cross Sections ◽  
3D Integration ◽  
Leakage Currents ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

Simplistic approach to alleviate noise coupling issues in 3D IC integration

2020 ◽  
Vol 33 ◽  
pp. 4007-4011 ◽  
Author(s):  
Dadaipally Pragathi ◽  
Ch Usha Kumari ◽  
M. Usha Rani ◽  
T. Santosh Kumar ◽  
Tatiparti Padma ◽  
...  
Keyword(s):  
3D Ic ◽  
Noise Coupling
Sign in / Sign up

Export Citation Format

Share Document