Wafer level packaging for high-brightness LED lighting with optimized thermal dissipation and optical performance

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001787-001817
Author(s):  
Liang Wang ◽  
Gabe Guevara ◽  
Rey Co ◽  
Ron Zhang ◽  
Roseann Alatorre
Keyword(s):  
Power Efficiency ◽  
Wavelength Conversion ◽  
Bonding Process ◽  
Light Extraction ◽  
Thermal Dissipation ◽  
Wafer Level ◽  
High Brightness ◽  
Led Lighting ◽  
Wafer Level Packaging ◽  
Packaging Structure

High-brightness LED lighting has gained high attention in the industry and its market share for general lighting has been rapidly expanding upon the continued progress on improving internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A lion share of cost of an LED module is incurred during the packaging processes after the emissive device stack has been fabricated. Also given the thin thickness of device stack, the packaging structure remains the bottleneck for thermal dissipation. We address these two key challenges with a novel wafer-level packaging structure integrated into the device stack, which enables maximal thermal dissipation rate from active device stack to substrate while allowing high aperture ratio and optimized light output. Our approach applies full wafer-level batch process from epitaxial growth all the way down to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. Initial prototypes of GaN based blue LED with big chip size have been fabricated without selective electrodes for minimal contact resistance, exhibiting high brightness at relatively low drive voltage (3.5V). As one key step in wafer level packaging, the wafer bonding process was characterized with Moire patterning and Topography and Deformation Measurement to understand the warpage profile and varying temperatures along both heat up and cool down paths, with simulation performed in guidance to final solution for compensating the warpage profile along the bonding process and afterwards. Different approaches were applied in learning the most effective bonding technique for this packaging structure. Further development is ongoing to improve the overall power efficiency and color quality, including optimal materials for ohmic contacts at both electrodes, current-spreading layer, large-area light extraction structure, and integrated phosphor material. This wafer-level packaging technology is scalable to large wafer size for high-throughput and low-cost manufacturing, to achieve both superior thermal management and optimized power efficiency.

High-brightness LEDs of big chip size on multi-layer interconnects with optimized thermal dissipation and optical performance

2014 ◽  
Vol 2014 (1) ◽  
pp. 000877-000881
Author(s):  
Liang Wang ◽  
Gabe Guevara ◽  
Grant Villavicencio ◽  
Roseann Alatorre ◽  
Hala Shaba ◽  
...  
Keyword(s):  
Flip Chip ◽  
Wavelength Conversion ◽  
Light Output ◽  
Light Extraction ◽  
Thermal Dissipation ◽  
High Yield ◽  
Wafer Level ◽  
High Brightness ◽  
Aperture Ratio ◽  
Chip Size

The market share of high-brightness LEDs in general lighting has been rapidly expanding mainly owing to the continued technological advances on internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, there remain some key breakthroughs to be made before LED lighting technology can be fully adopted into the broad market, with emphasis on efficient thermal dissipation, higher efficacy at high brightness, and low manufacturing cost. Higher brightness requires LEDs to be operated at higher current density which results in efficacy degradation due to droop behavior and thus higher power loss into heat and shorter lifetime. Therefore a highly efficient mechanism of thermal dissipation is needed for timely conduction of heat away from the high-power LED chip. For general lighting at high brightness, a large chip size is preferable. More importantly, with larger chip size, higher brightness can be achieved at much lower current density which leads to less degradation of efficacy. However simply increasing the die size of LEDs in wafer fabrication causes significant yield loss and thus hinders the adoption of big-chip LEDs. In this paper we propose a scalable approach to enable larger chip sizes for manufacturing high efficacy & high brightness LEDs at high yield and low cost. The metric of lower cost per lumen is necessary for LEDs to be competitive to traditional light sources like fluorescent lights in the consumer market segment. About 50% of the total LED production cost is consumed by the packaging processes after the emissive device stack being fabricated. Also given the minimal thickness of the device stack, the key bottleneck for thermal dissipation resides in the packaging structure and its interface to the device stack. We address these two key challenges with a novel wafer-level packaging structure of metal contacts forming a perimeter that is integrated into the device stack, which optimizes the thermal dissipation rate from the active device stack to substrate while allowing high aperture ratio and improved light output. Our approach applies a wafer-level batch process starting from LED fabrication to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. To improve the overall power efficiency, different materials have been selected for ohmic contacts and high reflectivity at p and n electrodes, and further developments continue to be implemented, including a current-spreading layer, large-area light extraction structure and integrated phosphor material. Flip chip packaging is chosen due to its advantage of full front-side emission, maximized aperture ratio, compact form factor, higher integration density and ease of wafer level processing. The substrates for flip chip packaging of LED chips are made of Si which was selected due to its relatively high thermal conductivity (149 W/m/K) and ease of fabrication with standard semiconductor processes. Multi-layer interconnects are patterned over the Si substrate with solder bumps built over the passivation openings for flip-chip assembly of multiple LED dies. The multi-layer dielectric stack of the substrate is designed to form dielectric mirror maximizing the reflection of emitted light back into the LED side for improved light output.

Packaging HB LEDs with Integrated Beamshaping

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001493-001514
Author(s):  
Thomas Hoeftmann
Keyword(s):  
Beam Shaping ◽  
Wafer Level ◽  
Consumer Market ◽  
High Brightness ◽  
Automotive Market ◽  
Wafer Level Packaging ◽  
Led Array ◽  
New Ideas ◽  
Application Fields ◽  
Glass Lenses

LED light will dominate in future a lot of application fields in everyday life and it already started not only in consumer market. Therefore more and more applications require new ideas and approaches for packaging to fulfill upgraded requirements for protection, reliability, beam shaping and cost reduction, especially for High Brightness (HB) LEDs in e.g. automotive and other markets. This presentation will give an overview about the developed monolithic window with integrated anti-glare shield for HB LED packaging used in the automotive market for low and high beam headlights and other special lighting functions of modern cars. Apart from the component protection, the monolithic window ensures that there is sufficient contrast and thus glare protection in the irradiation area of the LED array. In addition future packaging technologies will be introduced to provide 3D interconnection and beam shaping by glass lenses. All discussed packaging ideas will meet the requirement of vacuum tight wafer level packaging by building monolithic packaging boards or capping wafers made of micro processed silicon and glass material.

Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000263-000269 ◽  
Author(s):  
Jacinta Aman Lim ◽  
Vinayak Pandey
Keyword(s):  
Form Factor ◽  
Line Width ◽  
Graphics Processing Units ◽  
Power Efficiency ◽  
Building Blocks ◽  
Electrical Performance ◽  
Rf Power Amplifiers ◽  
Wafer Level ◽  
Central Processing ◽  
Wafer Level Packaging

Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.

LED & HB-LED Packaging: Technology & Marketing Trends

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001137-001176
Author(s):  
Jeff Perkins
Keyword(s):  
Cost Saving ◽  
Semiconductor Devices ◽  
Manufacturing Processes ◽  
Wafer Level ◽  
Full Spectrum ◽  
Packaging Technology ◽  
Led Lighting ◽  
Wafer Level Packaging ◽  
The Future ◽  
Technology Marketing

If LED lighting is to fulfill the promise it holds across all lighting segments, costs need to drop significantly and production volumes will need to double several times over in the coming years. To achieve both, cost improvements must happen at every level of manufacturing and manufacturing processes must evolve. When talking about LED device costs today, packaging holds the greatest cost saving opportunities. As with many semiconductor devices and for LED devices in particular, wafer level packaging will be a key cost saving move for the future. Much needs to be done and much is being done - this talk will take a look at the full spectrum of developments to bring LED into mainstream lighting applications.

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