Wafer level packaging for ultra thin (6 μm) high brightness LEDs using embedding technology

2013 ◽  
Author(s):  
J. Kleff ◽  
M. Topper ◽  
L. Dietrich ◽  
H. Oppermann ◽  
S. Herrmann
Keyword(s):  
Wafer Level ◽  
High Brightness ◽  
Wafer Level Packaging

Wafer level packaging for high-brightness LED lighting with optimized thermal dissipation and optical performance

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001787-001817
Author(s):  
Liang Wang ◽  
Gabe Guevara ◽  
Rey Co ◽  
Ron Zhang ◽  
Roseann Alatorre
Keyword(s):  
Power Efficiency ◽  
Wavelength Conversion ◽  
Bonding Process ◽  
Light Extraction ◽  
Thermal Dissipation ◽  
Wafer Level ◽  
High Brightness ◽  
Led Lighting ◽  
Wafer Level Packaging ◽  
Packaging Structure

High-brightness LED lighting has gained high attention in the industry and its market share for general lighting has been rapidly expanding upon the continued progress on improving internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A lion share of cost of an LED module is incurred during the packaging processes after the emissive device stack has been fabricated. Also given the thin thickness of device stack, the packaging structure remains the bottleneck for thermal dissipation. We address these two key challenges with a novel wafer-level packaging structure integrated into the device stack, which enables maximal thermal dissipation rate from active device stack to substrate while allowing high aperture ratio and optimized light output. Our approach applies full wafer-level batch process from epitaxial growth all the way down to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. Initial prototypes of GaN based blue LED with big chip size have been fabricated without selective electrodes for minimal contact resistance, exhibiting high brightness at relatively low drive voltage (3.5V). As one key step in wafer level packaging, the wafer bonding process was characterized with Moire patterning and Topography and Deformation Measurement to understand the warpage profile and varying temperatures along both heat up and cool down paths, with simulation performed in guidance to final solution for compensating the warpage profile along the bonding process and afterwards. Different approaches were applied in learning the most effective bonding technique for this packaging structure. Further development is ongoing to improve the overall power efficiency and color quality, including optimal materials for ohmic contacts at both electrodes, current-spreading layer, large-area light extraction structure, and integrated phosphor material. This wafer-level packaging technology is scalable to large wafer size for high-throughput and low-cost manufacturing, to achieve both superior thermal management and optimized power efficiency.

Packaging HB LEDs with Integrated Beamshaping

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001493-001514
Author(s):  
Thomas Hoeftmann
Keyword(s):  
Beam Shaping ◽  
Wafer Level ◽  
Consumer Market ◽  
High Brightness ◽  
Automotive Market ◽  
Wafer Level Packaging ◽  
Led Array ◽  
New Ideas ◽  
Application Fields ◽  
Glass Lenses

LED light will dominate in future a lot of application fields in everyday life and it already started not only in consumer market. Therefore more and more applications require new ideas and approaches for packaging to fulfill upgraded requirements for protection, reliability, beam shaping and cost reduction, especially for High Brightness (HB) LEDs in e.g. automotive and other markets. This presentation will give an overview about the developed monolithic window with integrated anti-glare shield for HB LED packaging used in the automotive market for low and high beam headlights and other special lighting functions of modern cars. Apart from the component protection, the monolithic window ensures that there is sufficient contrast and thus glare protection in the irradiation area of the LED array. In addition future packaging technologies will be introduced to provide 3D interconnection and beam shaping by glass lenses. All discussed packaging ideas will meet the requirement of vacuum tight wafer level packaging by building monolithic packaging boards or capping wafers made of micro processed silicon and glass material.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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