Silicon-based wafer-level packaging for cost reduction of high brightness LEDs

2011 ◽  
Author(s):  
Thomas Uhrmann ◽  
Thorsten Matthias ◽  
Paul Lindner
Keyword(s):  
Cost Reduction ◽  
Wafer Level ◽  
High Brightness ◽  
Wafer Level Packaging ◽  
Silicon Based

Wafer level packaging for high-brightness LED lighting with optimized thermal dissipation and optical performance

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001787-001817
Author(s):  
Liang Wang ◽  
Gabe Guevara ◽  
Rey Co ◽  
Ron Zhang ◽  
Roseann Alatorre
Keyword(s):  
Power Efficiency ◽  
Wavelength Conversion ◽  
Bonding Process ◽  
Light Extraction ◽  
Thermal Dissipation ◽  
Wafer Level ◽  
High Brightness ◽  
Led Lighting ◽  
Wafer Level Packaging ◽  
Packaging Structure

High-brightness LED lighting has gained high attention in the industry and its market share for general lighting has been rapidly expanding upon the continued progress on improving internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A lion share of cost of an LED module is incurred during the packaging processes after the emissive device stack has been fabricated. Also given the thin thickness of device stack, the packaging structure remains the bottleneck for thermal dissipation. We address these two key challenges with a novel wafer-level packaging structure integrated into the device stack, which enables maximal thermal dissipation rate from active device stack to substrate while allowing high aperture ratio and optimized light output. Our approach applies full wafer-level batch process from epitaxial growth all the way down to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. Initial prototypes of GaN based blue LED with big chip size have been fabricated without selective electrodes for minimal contact resistance, exhibiting high brightness at relatively low drive voltage (3.5V). As one key step in wafer level packaging, the wafer bonding process was characterized with Moire patterning and Topography and Deformation Measurement to understand the warpage profile and varying temperatures along both heat up and cool down paths, with simulation performed in guidance to final solution for compensating the warpage profile along the bonding process and afterwards. Different approaches were applied in learning the most effective bonding technique for this packaging structure. Further development is ongoing to improve the overall power efficiency and color quality, including optimal materials for ohmic contacts at both electrodes, current-spreading layer, large-area light extraction structure, and integrated phosphor material. This wafer-level packaging technology is scalable to large wafer size for high-throughput and low-cost manufacturing, to achieve both superior thermal management and optimized power efficiency.

Packaging HB LEDs with Integrated Beamshaping

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001493-001514
Author(s):  
Thomas Hoeftmann
Keyword(s):  
Beam Shaping ◽  
Wafer Level ◽  
Consumer Market ◽  
High Brightness ◽  
Automotive Market ◽  
Wafer Level Packaging ◽  
Led Array ◽  
New Ideas ◽  
Application Fields ◽  
Glass Lenses

LED light will dominate in future a lot of application fields in everyday life and it already started not only in consumer market. Therefore more and more applications require new ideas and approaches for packaging to fulfill upgraded requirements for protection, reliability, beam shaping and cost reduction, especially for High Brightness (HB) LEDs in e.g. automotive and other markets. This presentation will give an overview about the developed monolithic window with integrated anti-glare shield for HB LED packaging used in the automotive market for low and high beam headlights and other special lighting functions of modern cars. Apart from the component protection, the monolithic window ensures that there is sufficient contrast and thus glare protection in the irradiation area of the LED array. In addition future packaging technologies will be introduced to provide 3D interconnection and beam shaping by glass lenses. All discussed packaging ideas will meet the requirement of vacuum tight wafer level packaging by building monolithic packaging boards or capping wafers made of micro processed silicon and glass material.

Advanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-36 ◽  
Author(s):  
Elvino Da Silveira ◽  
Keith Best ◽  
Gurvinder Singh ◽  
Roger McCleary
Keyword(s):  
Cost Reduction ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Main Driver ◽  
Ratio Imaging ◽  
Advanced Packaging ◽  
High Yields ◽  
Line Space

For more than 50 years the semiconductor industry has pursued Moore's law, continuously improving device performance, reducing cost, and scaling transistor geometries down to where advanced CMOS has reached beyond the 10nm technology node. The commensurate increase in I/O count has created many challenges for device packaging which hitherto was considered low cost with simple solutions. It was once thought that old backend foundry lithography steppers could be used to address the new packaging requirements; which was true whilst the substrates remained in the traditional 300mm Silicon format. The recent unprecedented rapid growth in Fan Out Wafer Level Packaging (FOWLP) applications has introduced a more complicated landscape of process challenges, with no restriction on substrate format, where cost is the main driver and high yields are mandatory. This paper discusses the lithography process challenges that have ensued from disruptive FOWLP, and more recently the paradigm shift to Panel fan out Packaging. The work reports on lithography solutions for CD control over topography and high aspect ratio imaging of 2μm line/space RDL. In addition, the introduction of new inspection capabilities for defects and metrology is reported for both wafers and panels. The increase in lithography productivity and cost reduction provided by FOPLP is also discussed with production examples.

Precise underfill dispense in high-throughput chip-on-wafer packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Hanzhuang Liang
Keyword(s):  
Key Words ◽  
High Throughput ◽  
Cost Reduction ◽  
Flip Chip ◽  
Microelectronic Packaging ◽  
Portable Devices ◽  
Wafer Level ◽  
Flip Chips ◽  
Wafer Level Packaging ◽  
One Year

In today's microelectronic packaging, components are continuously designed smaller and assembled more densely to allow more functions to fit into compact portable devices. To enable this trend, more manufacturers are using flip chips that have more I/O's and smaller bumps sizes. This has introduced underfill dispensing that fills the gap between the flip chip and the substrate with polymer epoxy to help reduce thermal and mechanical stress at the bonding interface. In device packaging, the demands for cost reduction and miniaturization encourage the use of wafer-level packaging, such as the chip-on-wafer process. As a result, the challenges to this process have grown exponentially, and so have the challenges to underfill dispensing. For example, to package a device with a chip-last process, the keep-out-zone (KOZ) for underfill epoxy placement to nearby components is shrinking, e.g. from 700um to 300–500um within one year. A high-precision, high-throughput underfill dispensing process has been developed to conquer these challenges. This underfill process is being used in production for chip-on-wafer packaging. In one example, underfill must be dispensed within KOZ 300–500um at UPH 4000. New equipment and new dispensing techniques are under development to further push the limit on higher throughput and precision. Key words: underfill, dispense, microelectronic packaging, device packaging, wafer-level packaging, chip-on-wafer, chip-last, keep-out-zone, precision, throughput

Wafer Level Packaging of Compound Semiconductors

2010 ◽  
Vol 7 (3) ◽  
pp. 152-159
Author(s):  
Andrew Strandjord ◽  
Thorsten Teutsch ◽  
Axel Scheffler ◽  
Bernd Otto ◽  
Anna Paat ◽  
...  
Keyword(s):  
Bulk Material ◽  
Semiconductor Devices ◽  
Compound Semiconductors ◽  
Compound Semiconductor ◽  
Silicon Wafers ◽  
Manufacturing Companies ◽  
Wafer Level ◽  
Contract Manufacturing ◽  
Wafer Level Packaging ◽  
Silicon Based

The microelectronics industry has implemented a number of different wafer level packaging (WLP) technologies for high volume manufacturing, including: UBM deposition, solder bumping, wafer thinning, and dicing. These technologies were successfully developed and implemented at a number of contract manufacturing companies, and then licensed to many of the semiconductor manufacturers and foundries. The largest production volumes for these technologies are for silicon-based semiconductors. Continuous improvements and modifications to these WLP processes have made them compatible with the changes observed over the years in silicon semiconductor technologies. These industry changes include: the move from aluminum to copper interconnect metallurgy, increases in wafer size, decreases in pad pitch, and the use of Low-K dielectrics. In contrast, the direct transfer of these WLP technologies to compound semiconductor devices, like GaAs, SiC, InP, GaN, and sapphire; has been limited due to a number of technical compatibility issues, several perceived compatibility issues, and some business concerns From a technical standpoint, many compound semiconductor devices contain fragile air bridges, gold bond pads, topographical cavities and trenches, and have a number of unique bulk material properties which are sensitive to the mechanical and chemical processes associated with the standard WLP operations used for silicon wafers. In addition, most of the newer contract manufacturing companies and foundries have implemented mostly 200 and 300 mm wafer capabilities into their facilities. This limits the number of places that one can outsource the processing of 100 and 150 mm compound semiconductor wafers. Companies that are processing large numbers of silicon based semiconductor wafers at their facilities are reluctant to process many of these compound semiconductors because there is a perceived risk of cross contamination between the different wafer materials. Companies are not willing to risk their current business of processing silicon wafers by introducing these new materials into existing process flows. From a business perspective, many companies are reluctant to take the liability risks associated with some of the very high-value compound semiconductors. In addition, the volumes for many of the compound semiconductor devices are very small compared with silicon based devices, thus making it hard to justify interruption in the silicon wafer flows to accommodate these lower volume products. In spite of these issues and perceptions, the markets for compound semiconductors are expanding. Several high profile examples include the increasing number of frequency and power management devices going into cell phones, light emitting diodes, and solar cells The strategy for the work described in this paper is to protect all structures and surfaces with either a spin-on resist or a laminated film during each step in the process flow. These layers will protect the wafer from mechanical and chemical damage, and at the same time protect the fab from contamination by the compound semiconductor.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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