Laser de-bonding process development of glass substrate for Fan-out wafer level packaging

2016 ◽  
Author(s):  
Hsiang Yao Hsiao ◽  
Soon Wee Ho ◽  
Boon Long Lau
Keyword(s):  
Glass Substrate ◽  
Process Development ◽  
Bonding Process ◽  
Wafer Level ◽  
Wafer Level Packaging

A New Wafer Level Packaging Approach: Encapsulation, Metallization and Laser Structuring for Advanced System in Package Manufacturing

2005 ◽  
Vol 127 (1) ◽  
pp. 1-6 ◽  
Author(s):  
K.-F. Becker ◽  
T. Braun ◽  
A. Neumann ◽  
A. Ostmann ◽  
E. Coko ◽  
...  
Keyword(s):  
System Design ◽  
Process Development ◽  
Functional System ◽  
Single Chip ◽  
Wafer Level ◽  
Microelectronics Packaging ◽  
Flip Chips ◽  
Wafer Level Packaging ◽  
Electroless Process ◽  
Lead Free Solders

One of the general trends in microelectronics packaging is the constant miniaturization of devices. This has led to the development of maximum miniaturization of components on Si level, i.e., CSPs and Flip Chips. To further integrate more functionality into devices, and to further increase the degree of miniaturization, packaging development focus is switching from single chip packaging to the realization of systems in package, SiPs. Two main approaches do exist to realize this goal: one is to integrate all components into one dedicated package, yielding maximum miniaturization for a special application, but little flexibility as far as system design is concerned. The other is to create modular stackable components that can be assembled into a functional system. This integrates both flexibility in system design by exchangeable components and increased reliability potential, as single components can be tested separately. This last approach was considered a promising choice for the generation of SiPs. Within this paper a packaging process is introduced that allows the wafer level manufacturing of stackable, encapsulated devices. Using a transfer molded epoxy demonstrator, a proof-of-concept is performed showing the feasibility of the stackable package approach. This is achieved by combining wafer level encapsulation and molded interconnect device technology. An electroless process for metallization and laser techniques for structuring the metallization layer have been applied to generate structures for reliable interconnects capable for the use of lead-free solders. Summarized, this paper presents the process development and feasibility analysis of wafer level packaging technologies for modular SiP solutions based on a duromer MID approach.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 000809-000825
Author(s):  
Bernard Adams ◽  
Won Kyung Choi ◽  
Duk Ju Na ◽  
Andy Yong ◽  
Seung Wook Yoon ◽  
...  
Keyword(s):  
Line Width ◽  
High Performance ◽  
Process Development ◽  
Data Access ◽  
Electrical Performance ◽  
Logic Device ◽  
Wafer Level ◽  
Component Level ◽  
Wafer Level Packaging ◽  
Fine Pitch

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

Wafer level packaging for high-brightness LED lighting with optimized thermal dissipation and optical performance

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001787-001817
Author(s):  
Liang Wang ◽  
Gabe Guevara ◽  
Rey Co ◽  
Ron Zhang ◽  
Roseann Alatorre
Keyword(s):  
Power Efficiency ◽  
Wavelength Conversion ◽  
Bonding Process ◽  
Light Extraction ◽  
Thermal Dissipation ◽  
Wafer Level ◽  
High Brightness ◽  
Led Lighting ◽  
Wafer Level Packaging ◽  
Packaging Structure

High-brightness LED lighting has gained high attention in the industry and its market share for general lighting has been rapidly expanding upon the continued progress on improving internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, some key breakthroughs must be made before this technology can be fully adopted into the broad market, such as efficient thermal dissipation and low manufacturing cost. A lion share of cost of an LED module is incurred during the packaging processes after the emissive device stack has been fabricated. Also given the thin thickness of device stack, the packaging structure remains the bottleneck for thermal dissipation. We address these two key challenges with a novel wafer-level packaging structure integrated into the device stack, which enables maximal thermal dissipation rate from active device stack to substrate while allowing high aperture ratio and optimized light output. Our approach applies full wafer-level batch process from epitaxial growth all the way down to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. Initial prototypes of GaN based blue LED with big chip size have been fabricated without selective electrodes for minimal contact resistance, exhibiting high brightness at relatively low drive voltage (3.5V). As one key step in wafer level packaging, the wafer bonding process was characterized with Moire patterning and Topography and Deformation Measurement to understand the warpage profile and varying temperatures along both heat up and cool down paths, with simulation performed in guidance to final solution for compensating the warpage profile along the bonding process and afterwards. Different approaches were applied in learning the most effective bonding technique for this packaging structure. Further development is ongoing to improve the overall power efficiency and color quality, including optimal materials for ohmic contacts at both electrodes, current-spreading layer, large-area light extraction structure, and integrated phosphor material. This wafer-level packaging technology is scalable to large wafer size for high-throughput and low-cost manufacturing, to achieve both superior thermal management and optimized power efficiency.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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