Improvement of Plated Copper Adhesion in Glass Interposer Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001807-001826
Author(s):  
Simon Bamberg ◽  
Vijay Sukumaran ◽  
Venky Sundaram ◽  
Rao Tummala ◽  
Johannes Etzkorn ◽  
...  
Keyword(s):  
Low Cost ◽  
Polymer Surface ◽  
Electrical Performance ◽  
Organic Substrates ◽  
Thin Glass ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Glass Interface ◽  
Wet Chemical ◽  
Chemical Metallization

Glass interposers offer a compelling alternative to silicon interposers with highest I/Os and excellent electrical performance, with potential for low cost from large panel processing. For sub-32nm IC nodes and 3D-IC packages at fine I/O pitch, organic substrates are reaching their limits in terms of I/Os, design rules and CTE mismatch. Glass offers the best combination of electrical insulation, dimensional stability, CTE match to Si ICs, and flat, smooth surfaces for ultra-fine line lithography. The biggest challenge in glass interposers is the formation and metallization of ultra-fine pitch through vias. The formation of small via diameters in thin glass substrate have been demonstrated. The focus of this paper will be on wet metallization of glass interposer with through via, and addressing the challenge of providing reliable adhesion on the copper-to-glass interface. Two main approaches are currently pursued in the wet-chemical metallization of glass interposers: the electroless and electrolytic copper deposition on a) bare glass with photo-structured or laser-ablated through vias and b) the deposition on an intermediate polymer surface layer, requiring glass metallization only on the via sidewalls. Therefore, in addition to the analysis and optimization of adhesion-improving techniques on different glass types, their performance on different polymer liners is also assessed. The techniques include surface conditioning with cationic polyectrolytes and deposition of silica. The effect of the above surface pretreatments on plated copper adhesion is analyzed and the results provide guidelines for reliable glass interposer TPV metallization.

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

2015 ◽  
Vol 2015 (1) ◽  
pp. 000379-000385 ◽  
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Additive Process ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Compliant Stress-Engineered Interconnects for Next-Generation Packaging

2004 ◽  
Author(s):  
Kevin M. Klein ◽  
Suresh K. Sitaraman
Keyword(s):  
Life Stress ◽  
Low Cost ◽  
Intrinsic Stress ◽  
Wafer Level ◽  
Element Analysis ◽  
Operational Conditions ◽  
Technology Roadmap ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Future Demands

Future demands of microelectronic packing include increasing input/output (I/O) densities, providing high frequency capabilities, and maintaining sufficient reliability while keeping costs minimal. Organic materials with Coefficients of Thermal Expansions (CTE) over four times greater than silicon will continue to be used as future substrate materials because of their low cost. Consistent with the International Technology Roadmap for Semiconductors (ITRS, 2003), chip-to-substrate interconnects will need to have a pitch approximately equal to 40μm by the year 2012 and be able to accommodate the silicon and organic CTE mismatch without resorting to expensive reliability solutions. The demand for fine pitch chip-to-substrate interconnects combined with the CTE mismatch, creates significant demands for overall interconnect compliance as means to ensure reliability, through increasing fatigue life. Stress-engineered compliant off-chip interconnects are capable meeting future interconnect demands. Such interconnects are fabricated from stress-engineered metal thin-films using traditional IC fabrication methods and can be integrated with wafer level packing. A systematic design approach has been used to optimize interconnect geometry for use with estimated operational conditions. Finite Element Analysis (FEA) and Regression modeling have been used to create macro-models of interconnect behavior to assist in the optimization of the geometric design. Copper and Copper-Molybdenum are considered as interconnect material and the development intrinsic stress within copper is investigated via sputter deposition.

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

Low Cost Glass Interposer Development

2014 ◽  
Vol 2014 (1) ◽  
pp. 000397-000401 ◽  
Author(s):  
Yu-Hua Chen ◽  
Shaun Hsu ◽  
Urmi Ray ◽  
Ravi Shenoy ◽  
Kwan-Yu Lai ◽  
...  
Keyword(s):  
Low Cost ◽  
Organic Substrate ◽  
High Density ◽  
Organic Substrates ◽  
Test Vehicle ◽  
Thin Glass ◽  
Panel Size ◽  
Low Dielectric ◽  
Ic Packaging ◽  
Core Thickness

For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, managing the substrate warpage becomes critical. Traditional organic substrates may face several challenges for high density I/Os with very fine line interconnections. Glass is one of the candidates that can be used in substrate industry. The infrastructure of glass for LCD industry has already been developed for many years. Glass also has several superior properties than other substrate candidates, such as large panel size availability, adjustable CTE, high modulus, low dielectric constant, low dielectric loss and high insulating ability. In this paper, we successfully demonstrate early manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel of thickness of 200μm in 508mm μ 508mm panel size format and under the IC substrate manufacturing environment. Fabrication and electrical results of a test vehicle are documented. The test vehicle includes daisy chains that are connected with 100μm diameter through glass via (TGV) in a 200μm thick glass. The laser via in via technology was adopted for double side electrical connection. The copper line width/space of 8/8μm was demonstrated. The total thickness of 4 layers test vehicle is about 390μm. The warpage of glass in comparison with an organic substrate (BT) with 200μm core thickness is 3X better. Further work is needed to develop, fine tune and assess the detailed manufacturability and reliability concerns. Based on this work, it is clear that the potential of glass in IC packaging and integration is tremendous in diverse applications for substrate warpage enhancement.

Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch

2016 ◽  
Vol 13 (3) ◽  
pp. 128-135
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses ◽  
Low Permittivity

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates > 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Quality and Reliability of 3D TSV Interposer and Fine Pitch Solder Micro-bumps for 28nm Technology

2011 ◽  
Vol 2011 (1) ◽  
pp. 000189-000192 ◽  
Author(s):  
Bahareh Banijamali ◽  
Raghunandan Chaware ◽  
Suresh Ramalingam ◽  
Myongseob Kim
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Reliability ◽  
Three Dimensional ◽  
Electrical Performance ◽  
Related Factors ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Quality And Reliability

Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting significant industry attention. High density three dimensional (3D) interconnects formed by high aspect ratio through silicon via (TSV) and fine pitch solder micro bumps are presented in this paper. Different design/material related factors are evaluated during this study in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents some of the quality and reliability results as well as micro-bump and TSV resistance data. Furthermore, bake and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

Study on the Manufacture of Microfluidic Chip with Coated Glass

2012 ◽  
Vol 548 ◽  
pp. 254-257 ◽  
Author(s):  
Yan He ◽  
Bai Ling Huang ◽  
Yong Lai Zhang ◽  
Li Gang Niu
Keyword(s):  
Microfluidic Chip ◽  
Low Cost ◽  
Microfluidic Channel ◽  
Critical Factor ◽  
Wet Etching ◽  
Microfluidic Chips ◽  
Etching Technique ◽  
Chip Quality ◽  
Wet Chemical ◽  
Wet Chemical Etching

In this paper, a simple and facile technique for manufacturing glass-based microfluidic chips was developed. Instead of using expensive dry etching technology, the standard UV lithography and wet chemical etching technique was used to fabricate microchannels on a K9 glass substrate. The fabrication process of microfluidic chip including vacuum evaporation, annealing, lithography, and BHF (HF-NH4F-H2O) wet etching were investigated. Through series experiments, we found that anneal was the critical factor for chip quality. As a representative example, a microfluidic channel with 20 m of depth, and 80 m of width was successfully prepared, and the channel surfaces are quite smooth. These results present a simple, low cost, flexible and easy way to fabricate glass-based microfluidic chips.

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