High Frequency Electrical Performance and Thermo-Mechanical Reliability of Fine-Pitch, Copper-Metallized Through-Package-Vias (TPVs) in Ultra-Thin Glass Interposers

2017 ◽  
Author(s):  
Sukhadha Viswanathan ◽  
Tomonori Ogawa ◽  
Kaya Demir ◽  
Timothy B. Huang ◽  
P. Markondeya Raj ◽  
...  
Keyword(s):  
High Frequency ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Thin Glass ◽  
Fine Pitch

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

Improvement of Plated Copper Adhesion in Glass Interposer Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001807-001826
Author(s):  
Simon Bamberg ◽  
Vijay Sukumaran ◽  
Venky Sundaram ◽  
Rao Tummala ◽  
Johannes Etzkorn ◽  
...  
Keyword(s):  
Low Cost ◽  
Polymer Surface ◽  
Electrical Performance ◽  
Organic Substrates ◽  
Thin Glass ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Glass Interface ◽  
Wet Chemical ◽  
Chemical Metallization

Glass interposers offer a compelling alternative to silicon interposers with highest I/Os and excellent electrical performance, with potential for low cost from large panel processing. For sub-32nm IC nodes and 3D-IC packages at fine I/O pitch, organic substrates are reaching their limits in terms of I/Os, design rules and CTE mismatch. Glass offers the best combination of electrical insulation, dimensional stability, CTE match to Si ICs, and flat, smooth surfaces for ultra-fine line lithography. The biggest challenge in glass interposers is the formation and metallization of ultra-fine pitch through vias. The formation of small via diameters in thin glass substrate have been demonstrated. The focus of this paper will be on wet metallization of glass interposer with through via, and addressing the challenge of providing reliable adhesion on the copper-to-glass interface. Two main approaches are currently pursued in the wet-chemical metallization of glass interposers: the electroless and electrolytic copper deposition on a) bare glass with photo-structured or laser-ablated through vias and b) the deposition on an intermediate polymer surface layer, requiring glass metallization only on the via sidewalls. Therefore, in addition to the analysis and optimization of adhesion-improving techniques on different glass types, their performance on different polymer liners is also assessed. The techniques include surface conditioning with cationic polyectrolytes and deposition of silica. The effect of the above surface pretreatments on plated copper adhesion is analyzed and the results provide guidelines for reliable glass interposer TPV metallization.

Electrical-Thermal-Reliability Co-Design for TSV-Based 3D-ICs

2015 ◽  
Author(s):  
Tiantao Lu ◽  
Ankur Srivastava
Keyword(s):  
Mechanical Stress ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Thermal Reliability ◽  
Conduction Path ◽  
Placement Problem ◽  
Thermal Profile ◽  
3D Ic ◽  
3D Ics ◽  
Simulation Based

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.

Progress in Fabrication and Test of Glass Interposer Substrates

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001239-001258
Author(s):  
Aric Shorey ◽  
Scott Pollard
Keyword(s):  
Economies Of Scale ◽  
Functional Performance ◽  
Positive Impact ◽  
Coefficient Of Thermal Expansion ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Thin Glass ◽  
Reliability Performance ◽  
Downstream Processes ◽  
3D Applications

There is growing interest in applying glass as an interposer substrate for 2.5D/3D applications. Advantages of glass based solutions include significant opportunities for cost benefits by leveraging economies of scale as well as forming substrates at design thickness. A lot of work is being done to validate the value of glass as an interposer substrate. One important area is the electrical performance of glass relative to silicon. Because glass is an insulator, it is expected to have better electrical performance than silicon. Electrical characterization and electrical models demonstrate the advantages of the insulating properties of glass, and its positive impact on functional performance. Further advantages are anticipated in reliability performance, because of the ability to adjust thermal properties such as coefficient of thermal expansion (CTE) of glass. Progress in the ability to fabricate wafers and panels fully populated with through and blind holes has been reported. We describe the ability to leverage existing downstream processes such as via filling of both through and blind vias, as well as novel handling techniques to enable processing of thin glass. We also report progress in evaluating reliability through thermal cycle tests.

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

2015 ◽  
Vol 2015 (1) ◽  
pp. 000379-000385 ◽  
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Additive Process ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Analysis for Electrical Performance of Antenna Considering Gravity Deformation Based on Different Band and Elevation Angle

2017 ◽  
Vol 863 ◽  
pp. 266-272
Author(s):  
Kai Yu Hu ◽  
Kai Wang ◽  
Pei Zhang Wu ◽  
Yi Jiang
Keyword(s):  
High Frequency ◽  
High Reliability ◽  
Elevation Angle ◽  
Electrical Performance ◽  
High Frequency Band ◽  
Deep Space Exploration ◽  
Elevation Changes ◽  
Gain Loss ◽  
Deformation Error ◽  
Meaningful Data

Abstract.In order to ensure higher accuracy and better electrical performance of large antennas in future,this paper does some research for deformation of antenna’s reflector:modeling for 25m antenna and reappearing deformation when elevation changes every 15° just considering gravity by using ANSYS.Using results of simulation obtains deformation error curves with elevation changes, creates the conditions for compensating distortion and has a certain value. By using Ruze formula, deeply studies the regular about antenna’s electrical performance influenced by deformation because of elevation changes,obtains meaningful data and tables of relationship between elevation and parameters of electrical performance in nine bands of 25m antenna.It finds out that when working in high-frequency band, efficiency and gain loss of antenna will be more affected by elevation angle changes.Finally creates conditions for optimizing antenna parameters and performing high reliability tasks such as deep space exploration and aerospace communication.

scholarly journals A Miniaturized Transmitting LPDA Design for 2 MHz–30 MHz Uses

Sensors ◽  
2021 ◽  
Vol 21 (18) ◽  
pp. 6034
Author(s):  
Wenjun Zhu ◽  
Lixin Guo
Keyword(s):  
High Frequency ◽  
Optimization Methods ◽  
Directional Pattern ◽  
Electrical Performance ◽  
Impedance Bandwidth ◽  
Gain Bandwidth ◽  
Wave Simulation ◽  
Full Wave ◽  
Coefficient Optimization ◽  
Simulation Results

A miniaturized horizontal polarized high frequency transmitting LPDA is presented. In use of the dipole transformation and antenna coefficient optimization methods, a 65% reduction in the size was achieved with the electrical performance kept in a competitive level. Full-wave simulation results showed a stable directional pattern and lower VSWR over the impedance bandwidth of 2 to 30 MHz. The gain bandwidth can reach the range of 4–30 MHz, meanwhile, there is only minor degradation on gain in frequencies under 4 MHz.

scholarly journals Estimation of Electrical Performance of a Polymer Insulator with Deposited Moss on the Surface under Impulse Voltage Condition in Foggy Weather

2018 ◽  
Vol 4 (4) ◽  
pp. 1
Author(s):  
Farah Asyikin Abd Rahman ◽  
Izadi M ◽  
Kadir M.Z.A. Ab ◽  
Jasni J
Keyword(s):  
Electric Field ◽  
Field Distribution ◽  
High Frequency ◽  
Electric Field Distribution ◽  
Simulation Experiment ◽  
Electrical Performance ◽  
High Frequency Structure Simulator ◽  
Polymer Insulator ◽  
Pollution Flashover ◽  
Field Behaviour

This paper presents a study about electric field behaviour of 10kV polymer insulator with moss deposition under foggy condition. The aim of this simulation experiment was to determine if this field affect the initiation of pollution flashover. To study this effect, simulations were carried out using High Frequency Structure Simulator (HFSS). The simulation experiment includes the results of electric field distribution along the insulator and also the magnitude of electric field at three different locations in identifying the parts of the insulator’s surface that likely to initiate pollution flashover. The moss deposited polymer insulator displayed uniformed and considerably intense distribution of electric field with the clean insulator. The field result showed the likelihood in discharging a corona effect.  In short, the results indicated that electric field along the insulator surface would likely be influenced by moss deposition and foggy air.

Sign in / Sign up

Export Citation Format

Share Document