Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages

2010 ◽  
Author(s):  
Ki-Jae Song ◽  
Hunkyo Seo ◽  
Sang-hyun Ko
Keyword(s):  
Low Cost ◽  
Electrical Performance ◽  
Fine Pitch

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

Improvement of Plated Copper Adhesion in Glass Interposer Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001807-001826
Author(s):  
Simon Bamberg ◽  
Vijay Sukumaran ◽  
Venky Sundaram ◽  
Rao Tummala ◽  
Johannes Etzkorn ◽  
...  
Keyword(s):  
Low Cost ◽  
Polymer Surface ◽  
Electrical Performance ◽  
Organic Substrates ◽  
Thin Glass ◽  
Fine Pitch ◽  
Cte Mismatch ◽  
Glass Interface ◽  
Wet Chemical ◽  
Chemical Metallization

Glass interposers offer a compelling alternative to silicon interposers with highest I/Os and excellent electrical performance, with potential for low cost from large panel processing. For sub-32nm IC nodes and 3D-IC packages at fine I/O pitch, organic substrates are reaching their limits in terms of I/Os, design rules and CTE mismatch. Glass offers the best combination of electrical insulation, dimensional stability, CTE match to Si ICs, and flat, smooth surfaces for ultra-fine line lithography. The biggest challenge in glass interposers is the formation and metallization of ultra-fine pitch through vias. The formation of small via diameters in thin glass substrate have been demonstrated. The focus of this paper will be on wet metallization of glass interposer with through via, and addressing the challenge of providing reliable adhesion on the copper-to-glass interface. Two main approaches are currently pursued in the wet-chemical metallization of glass interposers: the electroless and electrolytic copper deposition on a) bare glass with photo-structured or laser-ablated through vias and b) the deposition on an intermediate polymer surface layer, requiring glass metallization only on the via sidewalls. Therefore, in addition to the analysis and optimization of adhesion-improving techniques on different glass types, their performance on different polymer liners is also assessed. The techniques include surface conditioning with cationic polyectrolytes and deposition of silica. The effect of the above surface pretreatments on plated copper adhesion is analyzed and the results provide guidelines for reliable glass interposer TPV metallization.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

PLA conductive filament for 3D printed smart sensing applications

2018 ◽  
Vol 24 (4) ◽  
pp. 739-743 ◽  
Author(s):  
Simone Luigi Marasso ◽  
Matteo Cocuzza ◽  
Valentina Bertana ◽  
Francesco Perrucci ◽  
Alessio Tommasi ◽  
...  
Keyword(s):  
Temperature Sensor ◽  
Low Cost ◽  
Conductive Polymer ◽  
Temperature Characteristic ◽  
Temperature Sensors ◽  
Electrical Performance ◽  
Content Type ◽  
Sensing Applications ◽  
3D Printed

Purpose This paper aims to present a study on a commercial conductive polylactic acid (PLA) filament and its potential application in a three-dimensional (3D) printed smart cap embedding a resistive temperature sensor made of this material. The final aim of this study is to add a fundamental block to the electrical characterization of printed conductive polymers, which are promising to mimic the electrical performance of metals and semiconductors. The studied PLA filament demonstrates not only to be suitable for a simple 3D printed concept but also to show peculiar characteristics that can be exploited to fabricate freeform low-cost temperature sensors. Design/methodology/approach The first part is focused on the conductive properties of the PLA filament and its temperature dependency. After obtaining a resistance temperature characteristic of this material, the same was used to fabricate a part of a 3D printed smart cap. Findings An approach to the characterization of the 3D printed conductive polymer has been presented. The major results are related to the definition of resistance vs temperature characteristic of the material. This model was then exploited to design a temperature sensor embedded in a 3D printed smart cap. Practical implications This study demonstrates that commercial conductive PLA filaments can be suitable materials for 3D printed low-cost temperature sensors or constitutive parts of a 3D printed smart object. Originality/value The paper clearly demonstrates that a new generation of 3D printed smart objects can already be obtained using low-cost commercial materials.

A TXV-less Packaging Platform for the Era of IoTs

2015 ◽  
Vol 2015 (1) ◽  
pp. 1-5 ◽  
Author(s):  
Dyi-Chung Hu ◽  
Yu-Min Lin ◽  
Hsiang Hung Chang ◽  
Tao-Chih Chang ◽  
Wei-Chung Lo ◽  
...  
Keyword(s):  
Low Cost ◽  
High Density ◽  
The Other ◽  
Electrical Performance ◽  
Test Vehicle ◽  
Technology Infrastructure ◽  
Fine Line ◽  
Large Panel ◽  
Line Technology ◽  
Test Chips

A new concept of packaging platform calls eHDF (embedded high density film), that without any TXVs is been proposed. The eHDF uses the technology from two categories; one utilize the semiconductor fine line technology infrastructure and the other takes the advantage of laminate organic large panel process infrastructure. Hence, the fine line, better electrical performance and low cost requirements can be addressed at the same time by the eHDF packaging platform. In this paper, a test vehicle based on eHDF structure will be built and modules assembly with test chips on eHDF substrate will be performed.

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

2015 ◽  
Vol 2015 (1) ◽  
pp. 000379-000385 ◽  
Author(s):  
Brett Sawyer ◽  
Yuya Suzuki ◽  
Zihan Wu ◽  
Hao Lu ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Speed ◽  
Metal Layer ◽  
Low Cost ◽  
Signal Propagation ◽  
Additive Process ◽  
Thin Glass ◽  
Fine Pitch ◽  
Data Rates ◽  
Insertion Losses

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Thermomechanical Design for Fine Pitch 3D-IC Packages

2012 ◽  
Vol 2012 (1) ◽  
pp. 001001-001009 ◽  
Author(s):  
Akihiro Horibe ◽  
Sayuri Kohara ◽  
Kuniaki Sueoka ◽  
Keiji Matsumoto ◽  
Yasumitsu Orii ◽  
...  
Keyword(s):  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
High Stress ◽  
High Viscosity ◽  
Thermomechanical Properties ◽  
Design Parameters ◽  
Element Analysis ◽  
Package Design ◽  
Fine Pitch ◽  
Silicon Vias

Low stress package design is one of the greatest challenges for the realization of reliable 3D integrated devices, since they are composed of elements susceptible to failures under high stress such as thin dies, metal through silicon vias (TSVs), and fine pitch interconnections. In variety of package components, an organic interposer is a key to obtain low cost modules with high density I/Os. However, the large mismatch in coefficient of thermal expansion (CTE) between silicon dies and organic laminates causes high stress in an organic package. The major parametric components in 3D devices are dies with /without Cu-TSVs, laminates, bumps, and underfill layers. Especially, the die thicknesses and underfill properties are ones of the parameters that give us some range to control as package design parameters. In general, the underfill material with a high modulus and a low CTE is effective in reducing the stress in solder interconnections between the Si die and the laminate. However, the filler content of underfill materials with such mechanical properties generally results in high viscosity. The use of high viscous materials in between silicon dies in 3D modules can degrade process ability in 3D integration. In this study, we show that the interchip underfills in 3D modules have a wider mechanical property window than in 2D modules even with fine pitch interconnections consisting mostly of intermetallic compounds (IMCs). Also the finite element analysis results show that the optimization of the structural or thermomechanical properties of organic laminates and interchip underfill contributes to reduction of stressing thinned silicon dies which may have some risks to the device performance.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

scholarly journals The effect of plasma functionalization on the print performance and time stability of graphite nanoplatelet electrically conducting inks

2020 ◽  
Author(s):  
Andrew Claypole ◽  
James Claypole ◽  
Tim Claypole ◽  
David Gethin ◽  
Liam Kilduff
Keyword(s):  
Printed Electronics ◽  
Low Cost ◽  
Electrical Performance ◽  
Graphite Nanoplatelets ◽  
Interparticle Interactions ◽  
Electrically Conducting ◽  
Wide Range ◽  
Oscillatory Rheology ◽  
The Stability ◽  
Plasma Functionalization

Abstract Carbon-based pastes and inks are used extensively in a wide range of printed electronics because of their widespread availability, electrical conductivity and low cost. Overcoming the inherent tendency of the nano-carbon to agglomerate to form a stable dispersion is necessary if these inks are to be taken from the lab scale to industrial production. Plasma functionalization of graphite nanoplatelets (GNP) adds functional groups to their surface to improve their interaction with the polymer resin. This offers an attractive method to overcome these problems when creating next generation inks. Both dynamic and oscillatory rheology were used to evaluate the stability of inks made with different loadings of functionalized and unfunctionalized GNP in a thin resin, typical of a production ink. The rheology and the printability tests showed the same level of dispersion and electrical performance had been achieved with both functionalized and unfunctionalized GNPs. The unfunctionalized GNPs agglomerate to form larger, lower aspect particles, reducing interparticle interactions and particle–medium interactions. Over a 12-week period, the viscosity, shear thinning behavior and viscoelastic properties of the unfunctionalized GNP inks fell, with decreases in viscosity at 1.17 s−1 of 24, 30, 39% for the ϕ = 0.071, 0.098, 0.127 GNP suspensions, respectively. However, the rheological properties of the functionalized GNP suspensions remained stable as the GNPs interacted better with the polymer in the resin to create a steric barrier which prevented the GNPs from approaching close enough for van der Waals forces to be effective.

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