Effects of Under-Fill Curing on Substrate Warpage

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001857-001875
Author(s):  
Robert L. Hubbard
Keyword(s):  
Flip Chip ◽  
Heat Processing ◽  
Complex Nature ◽  
Optimum Conditions ◽  
Model Studies ◽  
Convection Oven ◽  
Die Surface ◽  
Thermal Data ◽  
Die Stress ◽  
Low K

The formulation of flip-chip under-fill adhesives has become more critical to avoid stress-induced cracking at the solder ball interfaces farthest from the center of the die (neutral point) and of the low-k dielectric layers on the die surface. Single die packages, multiple die packages, and thin core-less substrates have now become so warped as to make the ball attach and board attach processes difficult. Recommended under-fill supplier cure profiles are generally accepted without much modification. This work compares the stress-induced substrate warpage developed in flip-chip assemblies using seven different under-fills from three different suppliers. Both low and high Tg materials from each supplier are included. Standard isothermal convection oven cures and variable frequency microwave (VFM) cures were compared with programmed multi-step cure profiles to determine the optimum conditions for lowest die stress and substrate warpage. Due to the complex nature of modern under-fill mixtures and the significant differences in the heating mechanisms, the thermo-mechanical properties of the cured resins are not easily interpreted with respect to cause and effect, however some of the results are surprising. The differences in warpage between “full cure” and “cure to Tg” profiles for both heating methods are demonstrated and discussed with respect to potential adhesive network structures from model studies and actual thermal data. Recommendations are made for dispense temperatures, ramp rates, soak temperatures, and extended curing. These effects are important when assemblies face additional heat processing such as subsequent solder reflow.

Stress Measurement Errors in Flip Chip Packages Using Multi-Element Sensor Rosettes on (111) Silicon

2009 ◽  
Author(s):  
Richard C. Jaeger ◽  
Jeffrey C. Suhling ◽  
Safina Hussain ◽  
Jordan C. Roberts ◽  
Mohammad A. Motalab ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Measurement Errors ◽  
Flip Chip ◽  
Stress Measurement ◽  
Element Model ◽  
Die Surface ◽  
Die Stress ◽  
Many Sources ◽  
Stress Dependent ◽  
Temperature Errors

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. A previous paper initated a study of the errors in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients and temperature. In this work, we apply the earlier results to an analysis of the sensitivities and errors in the extracted stresses on an integrated circuit die in a flip-chip package. A finite-element model for a basic flip-chip configuration is utilized to estimate the stress across the surface of the silicon die. These results are used to evaluate the stress sensitivities to coefficient and temperature errors throughout the die surface. The sensitivities are stress dependent and vary widely from very small to very large over the die surface. The results confirm that temperature compensated rosette configurations should be utilized whenever possible.

Nature of Package-Induced Deformation and the Risk of Fracture in Low-k Dielectric Stacks

2011 ◽  
Author(s):  
Hung-Yun Lin ◽  
Abhishek Tambat ◽  
Ian Claydon ◽  
Ganesh Subbarayan ◽  
Dae Young Jung ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Temperature Dependent ◽  
Interlayer Dielectric ◽  
Risk Of Fracture ◽  
Finite Element Software ◽  
Reflow Temperature ◽  
Deformation State ◽  
Die Surface ◽  
Low K

The risk of fracture in Interlayer Dielectric (ILD) stack is evaluated for various configurations of flip-chip packages in this paper. A novel analysis on the mechanical behavior of package with a focus on die surface provides the insights into the critical deformation state as well as its location. In Controlled Collapse Chip Connection (C4) process, the reflow phase involves a cooling of the entire package from the reflow temperature to room temperature, and is critical for package induced die cracking (Chip-Package Interaction or CPI). We use commercial finite element software ABAQUS to construct local sub-models of ILD region from global models of a representative 3-D package with component materials modeled as being temperature dependent elastic or elasto-plastic as appropriate. The risk of ILD fracture is systematically investigated using the described approach.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump

2011 ◽  
Vol 2011 (1) ◽  
pp. 000828-000836
Author(s):  
Yasumitsu Orii ◽  
Kazushige Toriyama ◽  
Sayuri Kohara ◽  
Hirokazu Noma ◽  
Keishi Okamoto ◽  
...  
Keyword(s):  
Aging Process ◽  
Flip Chip ◽  
Fem Simulation ◽  
Organic Substrate ◽  
Organic Substrates ◽  
Cross Sectional ◽  
Pillar Height ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Low K

The electromigration behavior of 80μm bump pitch C2 (Chip Connection) interconnection is studied and discussed. C2 is a peripheral ultra fine pitch flip chip interconnection technique with solder capped Cu pillar bumps formed on Al pads that are commonly used in wirebonding technique. It allows us an easy control of the space between dies and substrates simply by varying the Cu pillar height. Since the control of the collapse of the solder bumps is not necessary, the technology is called the “C2 (Chip Connection)”. C2 bumps are connected to OSP surface treated Cu substrate pads on an organic substrate by reflow with no-clean process, hence the C2 is a low cost ultra fine pitch flip chip interconnection technology. The reliability tests on the C2 interconnection including thermal cycle tests and thermal humidity bias tests have been performed previously. However the reliability against electromigration for such small flip chip interconnections is yet more to investigate. The electromigration tests were performed on 80μm bump pitch C2 flip chip interconnections. The interconnections with two different solder materials were tested: Sn-2.5Ag and Sn100%. The effect of Ni layers electroplated onto the Cu pillar bumps on electromigration phenomena is also studied. From the cross-sectional analyses of the C2 joints after the tests, it was found that the presence of intermetallic compound (IMC) layers reduces the atomic migration of Cu atoms into Sn solder. The analyses also showed that the Ni layers are effective in reducing the migration of Cu atoms into solder. In the C2 joints, the under bump metals (UBMs) are formed by sputtered Ti/Cu layers. The electro-plated Cu pillar height is 45μm and the solder height is 25μm for 80μm bump pitch. The die size is 7.3-mm-square and the organic substrate is 20-mm-square with a 4 layer-laminated prepreg with thickness of 310μm. The electromigration test conditions ranged from 7 to 10 kA/cm2 with temperature ranging from 125 to 170°C. Intermetallic compounds (IMCs) were formed prior to the test by aging process of 2,000hours at 150°C. We have studied the effect of IMC layers on electromigration induced phenomena in C2 flip chip interconnections on organic substrates. The study showed that the IMC layers in the C2 joints formed by aging process can act as barrier layers to prevent Cu atoms from diffusing into Sn solder. Our results showed potential for achieving electromigration resistant joints by IMC layer formation. The FEM simulation results show that the current densities in the Cu pillar and the solder decrease with increasing Cu pillar height. However an increase in Cu pillar height also leads to an increase in low-k stress. It is important to design the Cu pillar structure considering both the electromigration performance and the low-k stress reduction.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

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