A Systematic Approach to Qualification of 90 nm Low-K Flip-Chip Packaging

2006 ◽  
Author(s):  
U. Vissa ◽  
N. Butel ◽  
J. Rowatt ◽  
C. Thielen ◽  
D. McCann ◽  
...  
Keyword(s):  
Flip Chip ◽  
Systematic Approach ◽  
Flip Chip Packaging ◽  
Low K

Analysis of flip-chip packaging challenges on copper/low-k interconnects

2003 ◽  
Vol 3 (4) ◽  
pp. 111-118 ◽  
Author(s):  
L.L. Mercado ◽  
C. Goldberg ◽  
Shun-Meen Kuo ◽  
Tien-Yu Lee ◽  
S.K. Pozder
Keyword(s):  
Flip Chip ◽  
Flip Chip Packaging ◽  
Low K

Improvement of ELK Reliability in Flip Chip Packages using Bond-on-Lead (BOL) Interconnect Structure

2010 ◽  
Vol 2010 (1) ◽  
pp. 000197-000203 ◽  
Author(s):  
Eric Ouyang ◽  
MyoungSu Chae ◽  
Seng Guan Chow ◽  
Roger Emigh ◽  
Mukul Joshi ◽  
...  
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Low Cost ◽  
Reliability Testing ◽  
Element Simulation ◽  
Testing Data ◽  
Flip Chip Packaging ◽  
Solder Mask ◽  
The Cost ◽  
Low K

In this paper, a novel flip chip interconnect structure called Bond-On-Lead (BOL) and its ability to reduce stress in the sensitive sub-surface ELK (Extra Low K) layers of the die is presented. BOL is a new low cost flip chip packaging solution which was developed by STATSChipPAC to dramatically reduce the cost of flip chip packaging. The BOL solution allows for efficient substrate routing by virtue of the use of narrow BOL pads and the removal of solder mask in the area of the BOL pads, which eliminates the limitations associated with solder mask opening sizes and positional tolerances. In addition to the compelling cost benefits, modeling results are confirmed with empirical reliability testing data to show that BOL is superior to the traditional Bond-on-Capture Pad (BOC) configuration from a mechanical stress and reliability perspective. The focus of this paper is on the theoretical analysis of the stress, strain, and warpage associated with the BOL configuration compared with the traditional BOC structure. For the package deformation, the global finite element method is used to simulate the package warpage. For the local bumping reliability, the focus is on the ELK layers which are the critical locations affecting the package's reliability. The local finite element simulation is conducted to compare the critical ELK layers stresses with BOL structure vs. with traditional BOC structure.

UBM integrity studies on copper/low-k dielectrics for fine pitch flip chip packaging

2004 ◽  
Author(s):  
Seung Wook Yoon ◽  
V. Kripesh ◽  
Wong Wai Kwan ◽  
Li Chao Yong ◽  
Chen Man Tong ◽  
...  
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Flip Chip Packaging ◽  
Low K

Effects of underfill materials on the reliability of low-K flip-chip packaging

2006 ◽  
Vol 46 (1) ◽  
pp. 155-163 ◽  
Author(s):  
K.M. Chen ◽  
D.S. Jiang ◽  
N.H. Kao ◽  
J.Y. Lai
Keyword(s):  
Flip Chip ◽  
Flip Chip Packaging ◽  
Low K

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

2004 ◽  
Vol 33 (10) ◽  
pp. 1144-1155 ◽  
Author(s):  
Seung Wook Yoon ◽  
Vaidyanathan Kripesh ◽  
Su Young Ji Jeffery ◽  
Mahadevan K. Iyer
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Flip Chip Packaging ◽  
Low K
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