Stress Measurement Errors in Flip Chip Packages Using Multi-Element Sensor Rosettes on (111) Silicon

2009 ◽  
Author(s):  
Richard C. Jaeger ◽  
Jeffrey C. Suhling ◽  
Safina Hussain ◽  
Jordan C. Roberts ◽  
Mohammad A. Motalab ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Measurement Errors ◽  
Flip Chip ◽  
Stress Measurement ◽  
Element Model ◽  
Die Surface ◽  
Die Stress ◽  
Many Sources ◽  
Stress Dependent ◽  
Temperature Errors

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. A previous paper initated a study of the errors in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients and temperature. In this work, we apply the earlier results to an analysis of the sensitivities and errors in the extracted stresses on an integrated circuit die in a flip-chip package. A finite-element model for a basic flip-chip configuration is utilized to estimate the stress across the surface of the silicon die. These results are used to evaluate the stress sensitivities to coefficient and temperature errors throughout the die surface. The sensitivities are stress dependent and vary widely from very small to very large over the die surface. The results confirm that temperature compensated rosette configurations should be utilized whenever possible.

Impact of Piezoresistive Coefficient Uncertainty on Stress Measurement Using Silicon Multi-Resistor Sensor Rosettes

2008 ◽  
Author(s):  
Richard C. Jaeger ◽  
Chun-Hyung Cho ◽  
Safina Hussain ◽  
Jeffrey C. Suhling
Keyword(s):  
Integrated Circuit ◽  
Stress Measurement ◽  
Direct Analysis ◽  
Electronic Packages ◽  
Sources Of Error ◽  
Die Surface ◽  
Die Stress ◽  
Many Sources ◽  
Stress Dependent

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. However, error in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients has not been explored in detail. In this work, direct analysis of the sensitivities of the extracted stresses to uncertainties in the piezoresistive coefficients is presented. The sensitivities are found to be stress dependent and therefore vary widely from very small to very large over the die surface. The results indicate that temperature compensated rosette configurations should be utilized whenever possible. Study of these sensitivities may lead to new rosette optimizations.

Effects of Under-Fill Curing on Substrate Warpage

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001857-001875
Author(s):  
Robert L. Hubbard
Keyword(s):  
Flip Chip ◽  
Heat Processing ◽  
Complex Nature ◽  
Optimum Conditions ◽  
Model Studies ◽  
Convection Oven ◽  
Die Surface ◽  
Thermal Data ◽  
Die Stress ◽  
Low K

The formulation of flip-chip under-fill adhesives has become more critical to avoid stress-induced cracking at the solder ball interfaces farthest from the center of the die (neutral point) and of the low-k dielectric layers on the die surface. Single die packages, multiple die packages, and thin core-less substrates have now become so warped as to make the ball attach and board attach processes difficult. Recommended under-fill supplier cure profiles are generally accepted without much modification. This work compares the stress-induced substrate warpage developed in flip-chip assemblies using seven different under-fills from three different suppliers. Both low and high Tg materials from each supplier are included. Standard isothermal convection oven cures and variable frequency microwave (VFM) cures were compared with programmed multi-step cure profiles to determine the optimum conditions for lowest die stress and substrate warpage. Due to the complex nature of modern under-fill mixtures and the significant differences in the heating mechanisms, the thermo-mechanical properties of the cured resins are not easily interpreted with respect to cause and effect, however some of the results are surprising. The differences in warpage between “full cure” and “cure to Tg” profiles for both heating methods are demonstrated and discussed with respect to potential adhesive network structures from model studies and actual thermal data. Recommendations are made for dispense temperatures, ramp rates, soak temperatures, and extended curing. These effects are important when assemblies face additional heat processing such as subsequent solder reflow.

Interfacial Delamination in Plastic Encapsulated Integrated Circuits (Pics)

1996 ◽  
Vol 445 ◽  
Author(s):  
Nickolaos Strifas ◽  
Aris Christou
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Stress Corrosion ◽  
Integrated Circuit ◽  
Point Of View ◽  
Acoustic Microscopy ◽  
Electrical Performance ◽  
Premature Failure ◽  
Interfacial Delamination ◽  
Die Surface

AbstractThe reliability of plastic packaged integrated circuits was assessed from the point of view of interfacial mechanical integrity. It is shown that the effect of structural weaknesses caused by poor bonding, voids, microcracks or delamination may not be evident in the electrical performance characteristics, but may cause premature failure. Acoustic microscopy (C-SAM) was selected for nondestructive failure analysis of the plastic integrated circuit (IC) packages. Integrated circuits in plastic dual in line packages were initially subjected to temperature (25 °C to 85 °C) and humidity cycling (50 to 85 %) where each cycle was of one hour duration and for over 100 cycles and then analyzed. Delamination at the interfaces between the different materials within the package, which is a major cause of moisture ingress and subsequent premature package failure, was measured. The principal areas of delamination were found along the leads extending from the chip to the edge of the molded body and along the die surface itself. Images of the 3-D internal structure were produced that were used to determine the mechanism for a package failure. The evidence of corrosion and stress corrosion cracks in the regions of delamination was identified.

scholarly journals Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Ultrasonic Transducer ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Lateral Side ◽  
Membrane Thickness ◽  
Bonding Performance ◽  
Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

“Cleaning”- The Dirty Word in Packaging Assembly

2010 ◽  
Vol 2010 (1) ◽  
pp. 000742-000746
Author(s):  
Rich Brooks
Keyword(s):  
Thermal Energy ◽  
Integrated Circuit ◽  
Flip Chip ◽  
New Technologies ◽  
Cleaning Process ◽  
Maximum Performance ◽  
Low Profile ◽  
Total Process ◽  
Temperature And Pressure

A majority of the package assembly facilities are using only DI water to remove flux residue from under flip-chip devices, prior to an underfill process. As the new technologies are being implemented, not only has DI water reached its limitations, but some cleaning chemistries are not able to perform adequately to remove ALL of the flux residues. Complete cleaning and removal of the flux residues under low profile components are critical to maintain the reliability of the integrated circuit. Therefore, the cleaning process must be carefully examined and optimized to obtain maximum performance for removing the flux residues. The total cleaning process can be broken down into two subsets:Static Cleaning rate & Dynamic Cleaning rate The Static Cleaning rate is ability of the cleaning chemistry to remove or dissolve the residue in the absence of temperature and pressure. The Dynamic Cleaning rate involves the kinetic forces and energy to remove the residue. This includes the Thermal energy and Impingement energy required to remove the flux residue. The sum of these two cleaning rates (Static and Dynamic cleaning rates) equal the Total Process Cleaning rate (see formula below). This paper will review cleaning problems brought about with the implementation of the latest technologies and explain how the cleaning process can be optimized to guarantee the reliability of the assemblies.

Sputtered WSix for micromechanical structures

1995 ◽  
Vol 10 (7) ◽  
pp. 1710-1720 ◽  
Author(s):  
Muh-Ling Ger ◽  
Richard B. Brown
Keyword(s):  
Thin Films ◽  
Integrated Circuit ◽  
Elastic Moduli ◽  
Stress Measurement ◽  
Rutherford Backscattering Spectrometry ◽  
Thermal Coefficient ◽  
Deposition Pressure ◽  
Sputtered Films ◽  
Effect Transistor ◽  
Micromechanical Structures

Tungsten silicide (WSix) thin tilms have been investigated for use as integrated circuit interconnect and self-aligned MESFET (metal-semiconductor field-effect transistor) gates because of their low resistivity and thermal and chemical stability. These same characteristics make them interesting materials for prospective use in micromechanical structures. However, little information on residual stresses, elastic moduli, or other micromechanical properties has been available for refractory metal silicide thin films. This paper presents the morphology and stress characteristics of cosputtered WSix thin films, including crystal structure variations and orientation-dependent stresses, as a function of the deposition pressure. The compositions of WSix thin films were analyzed by Rutherford backscattering spectrometry (RBS). The biaxial elastic modulus and thermal coefficient of expansion were found for the sputtered films. Stress-measurement methods and annealing are discussed. Released diaphragms of different sizes and shapes, having controlled residual stress, have been fabricated.

Evaluate the Importance of Shear Modulus in Dynamic FEM of Flexible Pavement Considering AC Cross-Anisotropy

2016 ◽  
Author(s):  
Mesbah U. Ahmed ◽  
Rafiqul A. Tarefder
Keyword(s):  
Shear Modulus ◽  
Resilient Modulus ◽  
Vertical Plane ◽  
Element Model ◽  
Tire Pressure ◽  
Stress Strain ◽  
Viscoelastic Parameters ◽  
Cross Anisotropy ◽  
As Stress ◽  
Stress Dependent

Goal of this study is to evaluate the effect of shear modulus variation on pavement responses, such as stress-strain, under dynamic load incorporating the AC cross-anisotropy. A dynamic Finite Element Model (FEM) of an instrumented asphalt pavement section on Interstate 40 (I-40) near Albuquerque, New Mexico, is developed in ABAQUS to determine stress-strain under truck tire pressure. Laboratory dynamic modulus tests were conducted on the AC cores to determine the temperature and frequency varying modulus values along both vertical and horizontal directions. The test outcomes are used to produce cross-anisotropic and viscoelastic parameters. Resilient modulus tests are conducted on granular aggregates from base and subbase layer to determine the nonlinear elastic and stress-dependent modulus values. These material parameters are integrated to the FEM through a FORTRAN subroutine via User Defined Material (UMAT) in the ABAQUS. The developed FEM is validated using the pavement deflections and stress-strain data under Falling Weight Deflectometer (FWD) test. The validated dynamic FEM is simulated under the non-uniform vertical tire contact stress. For the parametric study to investigate the effect of shear modulus variation on pavement responses, the validated FEM is simulated by varying the shear modulus in the AC layer. The results show that the variation in shear modulus along a vertical plane barely affects the tensile strain at the bottom of the AC layer and vertical compressive strains in both AC and unbound layers.

Dual-Axis Hole-Drilling ESPI Residual Stress Measurements

2009 ◽  
Vol 132 (1) ◽  
Author(s):  
Gary S. Schajer ◽  
Michael Steinzig
Keyword(s):  
Residual Stress ◽  
Measurement Errors ◽  
Measurement Method ◽  
Stress Measurement ◽  
Experimental Tests ◽  
Optical Data ◽  
Hole Drilling ◽  
Similar Response ◽  
Plane Normal ◽  
Stress Components

A novel dual-axis ESPI hole-drilling residual stress measurement method is presented. The method enables the evaluation of all the in-plane normal stress components with similar response to measurement errors, significantly lower than with single-axis measurements. A numerical method is described that takes advantage of, and compactly handles, the additional optical data that are available from the second measurement axis. Experimental tests were conducted on a calibrated specimen to demonstrate the proposed method, and the results supported theoretical expectations.

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