scholarly journals New Power MOSFET with Beyond-1D-Limit RSP-BV Trade-Off and Superior Reverse Recovery Characteristics

Materials ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2581
Author(s):  
Meng Zhang ◽  
Baikui Li ◽  
Jin Wei
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Power Switching ◽  
Deep Trench ◽  
Trade Off ◽  
Power Mosfet ◽  
P Bodies ◽  
Recovery Performance

The application of conventional power metal-oxide-semiconductor field-effect transistor (MOSFET) is limited by the famous one-dimensional “silicon limit” (1D-limit) in the trade-off relationship between specific on-resistance (RSP) and breakdown voltage (BV). In this paper, a new power MOSFET architecture is proposed to achieve a beyond-1D-limit RSP-BV trade-off. Numerical TCAD (technology computer-aided design) simulations were carried out to comparatively study the proposed MOSFET, the conventional power MOSFET, and the superjunction MOSFET. All the devices were designed with the same breakdown voltage of ~550 V. The proposed MOSFET features a deep trench between neighboring p-bodies and multiple p-islands located at the sidewall and bottom of the trench. The proposed MOSFET allows a high doping concentration in the drift region, which significantly reduces its RSP compared to the conventional power MOSFET. The multiple p-islands split the electric field into multiple peaks and help the proposed MOSFET maintain a similar breakdown voltage to the conventional power MOSFET with the same drift region thickness. Another famous device technology, the superjunction MOSFET (SJ-MOSFET), also breaks the 1D-limit. However, the SJ-MOSFET suffers a snappy reverse recovery performance, which is a notorious drawback of SJ-MOSFET and limits the range of its application. On the contrary, the proposed MOSFET presents a superior reverse recovery performance and can be used in various power switching applications where hard commutation is required.

A Study on the Optimization of Deep-Trench Super Junction Metal Oxide Semiconductor Field-Effect Transistor

2021 ◽  
Vol 16 (5) ◽  
pp. 781-785
Author(s):  
Yoon-Young Huh ◽  
Jong-Mun Choi ◽  
Jung-Min Kim ◽  
Ey-Goo Kang ◽  
Hun-Suk Chung
Keyword(s):  
Power Consumption ◽  
Breakdown Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Devices ◽  
Deep Trench ◽  
Trade Off ◽  
Effect Transistor

Power metal oxide semiconductor field-effect transistor is a switching device designed to handle large power consumption; it enables fast switching, resulting in low power consumption. Power devices are used as important components that determine the operation and performance of electrically powered products such as home appliances, smartphones, and automobiles. Power devices must be able to block high voltage so that current does not flow in the off state, have no power consumption in the on state, and have a small resistance so that high current can flow. For high efficiency, power loss must be minimized and resistance must be reduced during the turn-on state. To increase the breakdown voltage, the thickness and resistivity of the N-drift region must be increased. However, owing to the trade-off relationship, as the breakdown voltage increases, the on-resistance also increases. The super junction structure was proposed to improve this trade-off relationship. In this study, a process simulation using TCAD tool was carried out. Similar to the multi-epitaxial process, the P-pillar was divided into several layers, and the value of each concentration was specified. Thus, the charge balance of the pillar regions was achieved. For the maximum breakdown voltage characteristics and minimum on-resistance characteristics of the deep-trench super junction MOSFET, an experiment was conducted to optimize the cell pitch and pillar of the super junction MOSFET using a five-deep trench.

scholarly journals 150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 504
Author(s):  
Feng-Tso Chien ◽  
Zhi-Zhe Wang ◽  
Cheng-Li Lin ◽  
Tsung-Kuei Kang ◽  
Chii-Wen Chen ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Integrated System ◽  
Oxide Semiconductor ◽  
Epitaxial Layers ◽  
Engineering Technology ◽  
Power Mosfet ◽  
Power Mosfets ◽  
Aided Design ◽  
State Resistance

A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

Study on 600V Super Junction Power MOSFET Optimization and Electric Characteristics Using Deep Trench Filling

2013 ◽  
Vol 663 ◽  
pp. 698-702
Author(s):  
Bum June Kim ◽  
Eun Sik Jung ◽  
Ey Goo Kang
Keyword(s):  
Breakdown Voltage ◽  
Power Supply ◽  
Power Supply System ◽  
Voltage Drop ◽  
Supply System ◽  
Power Switching ◽  
Deep Trench ◽  
Power Mosfet ◽  
Operation Characteristics ◽  
Better Than

Power MOSFET device driven by voltage is designed as a power switching device in large capacity power supply system. It is also widely used in converters and motor controllers. However, the on-resistance characteristic during the increase of breakdown voltage is a problem. The on-resistance of super junction power MOSFET is lower by 1/3 than existing planar power MOSFET on 600V basis. This study designed 600V planar MOSFET/super junction MOSFET and compared their operation characteristics for lower on-resistance and higher breakdown voltage. The result suggested that super junction power MOSFET is better than planar power MOSFET by having 40% better on-state voltage drop performance.

scholarly journals Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1469 ◽  
Author(s):  
Po-Lin Lin ◽  
Shen-Li Chen ◽  
Sheng-Kai Fan
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
Breakdown Voltage ◽  
Electrostatic Discharge ◽  
Reference Group ◽  
Lateral Diffusion ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Field Oxide ◽  
Latch Up

Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

Novel Advanced Analytical Design Tool for 4H-SiC VDMOSFET Devices

2017 ◽  
Vol 897 ◽  
pp. 529-532 ◽  
Author(s):  
Luigi di Benedetto ◽  
Gian Domenico Licciardo ◽  
Tobias Erlbacher ◽  
Anton J. Bauer ◽  
Alfredo Rubino
Keyword(s):  
Figure Of Merit ◽  
Gate Oxide ◽  
Design Tool ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Trade Off ◽  
Blocking Voltage ◽  
Wide Range ◽  
Source Voltage ◽  
Effect Transistor

An analytical tool to design 4H-SiC power vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor is proposed. The model optimizes, in terms of the doping concentration in the Drift–region, the trade–off between the ON–resistance, RON, and the maximum blocking voltage, VBL, that is the Drain-Source voltage for which the avalanche breakdown appears at the p+–well/n-DRIFT junction together with the breakdown of the Gate oxide. Finding such trade-off means to maximize, Figure-Of-Merit. Our results are based on a novel full–analytical model of the electric field in the Gate oxide, EOX, whose generality is ensured by the absence of fitting and empirical parameters. Model results are successfully compared with 2D–simulations covering a wide range of device performances.

scholarly journals Study of a SiC Trench MOSFET Edge-Termination Structure with a Bottom Protection Well for a High Breakdown Voltage

2020 ◽  
Vol 10 (3) ◽  
pp. 753
Author(s):  
Jee-Hun Jeong ◽  
Ju-Hong Cha ◽  
Goon-Ho Kim ◽  
Sung-Hwan Cho ◽  
Ho-Jun Lee
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Surface Region ◽  
Ring Structure ◽  
Oxide Semiconductor ◽  
Cross Sectional ◽  
Edge Termination ◽  
Additional Process ◽  
Aided Design ◽  
Sectional Structure

A novel edge-termination structure for a SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) power device is proposed. The key feature of the proposed structure is a periodically formed SiC trench with a bottom protection well (BPW) implantation region. The trench can be filled with oxide or gate materials. Indeed, it has almost the same cross-sectional structure as the active region of a SiC trench MOSFET. Therefore, there is little or no additional process loads. A conventional floating field ring (FFR) structure utilizes the spreading of the electric field in the periodically depleted surface region formed between a heavily doped equipotential region. On the other hand, in the trenched ring structure, an additional quasi-equipotential region is provided by the BPW region, which enables deeper and wider field-spreading profiles, and less field crowding at the edge region. The two-dimensional Technology Computer Aided Design (2D-TCAD) simulation results show that the proposed trenched ring-edge termination structures have an improved breakdown voltage compared to the conventional floating field ring structure.

A 69-mΩ 600-V-Class Hybrid JFET

2013 ◽  
Vol 740-742 ◽  
pp. 925-928 ◽  
Author(s):  
Satoru Akiyama ◽  
Haruka Shimizu ◽  
Natsuki Yokoyama ◽  
Tomohiro Tamaki ◽  
Sadayuki Koido ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Breakdown Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Low Voltage ◽  
Oxide Semiconductor ◽  
Deep Trench ◽  
Trench Structure ◽  
Effect Transistor ◽  
State Resistance

A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm2. Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

scholarly journals Analytical Breakdown Voltage Model for Partial SOI-LDMOS Transistor with Buried Oxide Step Structure

2021 ◽  
Author(s):  
Jagamohan Sahoo ◽  
Rajat Mahapatra
Keyword(s):  
Electric Field ◽  
Analytical Model ◽  
Breakdown Voltage ◽  
Point Of View ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Design Parameters ◽  
Drift Region ◽  
Two Dimensional ◽  
The Impact

Abstract We have developed a simple physics-based two-dimensional analytical Off-state breakdown voltage model of a PBOSS Silicon-On-Insulator Lateral Diffused Metal Oxide Semiconductor (SOI-LDMOS) transistor. The analytical model includes the expressions of surface potential and electric field distributions in the drift region by solving the 2D Poisson’s equation. The electric field at the Si-SiO2 surface is modified by creating additional electric field peaks due to the presence of the PBOSS structure. The uniformly distributed electric field results in improving the breakdown voltage. Further, the breakdown voltage is analytically obtained via critical electric field concept to quantify the breakdown characteristic. The model exploits the impact of the critical device design parameters such as thickness and length of the PBOSS structure, doping, and thickness of the drift region on the surface electric field and the breakdown voltage. The proposed model is verified by the results obtained from ATLAS two dimensional simulations. The analytical model is of the high potential from a physical and mathematical point of view to design high voltage SOI-LDMOS transistors for power switching applications.

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

2015 ◽  
Vol 1096 ◽  
pp. 514-519
Author(s):  
Yue Hu ◽  
Hao Wang ◽  
De Wen Wang ◽  
Cai Xia Du ◽  
Miao Miao Ma ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Impurity Atoms ◽  
Surface Field ◽  
Field Peak ◽  
Effect Transistor

A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an electric field peak in the surface of the device, which can reduce the surface field in the device and adjust the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance.

scholarly journals Gate Current and Snapback of 4H-SiC Thyristors on N+ Substrate for Power-Switching Applications

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 332
Author(s):  
Hojun Lee ◽  
Ogyun Seok ◽  
Taeeun Kim ◽  
Min-Woo Ha
Keyword(s):  
Numerical Simulation ◽  
Breakdown Voltage ◽  
Doping Concentration ◽  
Voltage Drop ◽  
Depletion Region ◽  
Drift Region ◽  
Power Switching ◽  
Gate Current ◽  
High Voltage Direct Current ◽  
Forward Voltage Drop

High-power switching applications, such as thyristor valves in a high-voltage direct current converter, can use 4H-SiC. The numerical simulation of the 4H-SiC devices requires specialized models and parameters. Here, we present a numerical simulation of the 4H-SiC thyristor on an N+ substrate gate current during the turn-on process. The base-emitter current of the PNP bipolar junction transistor (BJT) flow by adjusting the gate potential. This current eventually activated a regenerative action of the thyristor. The increase of the gate current from P+ anode to N+ gate also decreased the snapback voltage and forward voltage drop (Vf). When the doping concentration of the P-drift region increased, Vf decreased due to the reduced resistance of a low P-drift doping. An increase in the P buffer doping concentration increased Vf owing to enhanced recombination at the base of the NPN BJT. There is a tradeoff between the breakdown voltage and forward characteristics. The breakdown voltage is increased with a decrease in concentration, and an increase in drift layer thickness occurs due to the extended depletion region and reduced peak electric field.

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