scholarly journals Gate Current and Snapback of 4H-SiC Thyristors on N+ Substrate for Power-Switching Applications

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 332
Author(s):  
Hojun Lee ◽  
Ogyun Seok ◽  
Taeeun Kim ◽  
Min-Woo Ha
Keyword(s):  
Numerical Simulation ◽  
Breakdown Voltage ◽  
Doping Concentration ◽  
Voltage Drop ◽  
Depletion Region ◽  
Drift Region ◽  
Power Switching ◽  
Gate Current ◽  
High Voltage Direct Current ◽  
Forward Voltage Drop

High-power switching applications, such as thyristor valves in a high-voltage direct current converter, can use 4H-SiC. The numerical simulation of the 4H-SiC devices requires specialized models and parameters. Here, we present a numerical simulation of the 4H-SiC thyristor on an N+ substrate gate current during the turn-on process. The base-emitter current of the PNP bipolar junction transistor (BJT) flow by adjusting the gate potential. This current eventually activated a regenerative action of the thyristor. The increase of the gate current from P+ anode to N+ gate also decreased the snapback voltage and forward voltage drop (Vf). When the doping concentration of the P-drift region increased, Vf decreased due to the reduced resistance of a low P-drift doping. An increase in the P buffer doping concentration increased Vf owing to enhanced recombination at the base of the NPN BJT. There is a tradeoff between the breakdown voltage and forward characteristics. The breakdown voltage is increased with a decrease in concentration, and an increase in drift layer thickness occurs due to the extended depletion region and reduced peak electric field.

scholarly journals Mobility Models Based on Forward Current-Voltage Characteristics of P-type Pseudo-Vertical Diamond Schottky Barrier Diodes

Micromachines ◽  
2020 ◽  
Vol 11 (6) ◽  
pp. 598
Author(s):  
Min-Woo Ha ◽  
Ogyun Seok ◽  
Hojun Lee ◽  
Hyun Ho Lee
Keyword(s):  
Schottky Barrier ◽  
Breakdown Voltage ◽  
Doping Concentration ◽  
Voltage Drop ◽  
Mobility Model ◽  
Mobility Models ◽  
Schottky Barrier Diodes ◽  
Forward Voltage ◽  
Forward Voltage Drop ◽  
P Type

Compared with silicon and silicon carbide, diamond has superior material parameters and is therefore suitable for power switching devices. Numerical simulation is important for predicting the electric characteristics of diamond devices before fabrication. Here, we present numerical simulations of p-type diamond pseudo-vertical Schottky barrier diodes using various mobility models. The constant mobility model, based on the parameter μconst, fixed the hole mobility absolutely. The analytic mobility model resulted in temperature- and doping concentration-dependent mobility. An improved model, the Lombard concentration, voltage, and temperature (CVT) mobility model, considered electric field-dependent mobility in addition to temperature and doping concentration. The forward voltage drop at 100 A/cm2 using the analytic and Lombard CVT mobility models was 2.86 and 5.17 V at 300 K, respectively. Finally, we used an empirical mobility model based on experimental results from the literature. We also compared the forward voltage drop and breakdown voltage of the devices, according to variations in p- drift layer thickness and cathode length. The device successfully achieved a low specific on-resistance of 6.8 mΩ∙cm2, a high breakdown voltage of 1190 V, and a high figure-of-merit of 210 MW/cm2.

Temperature-Dependent Characteristics of 4H-SiC Buried Grid JBS Diodes

2015 ◽  
Vol 821-823 ◽  
pp. 600-603 ◽  
Author(s):  
Jang Kwon Lim ◽  
S.A. Reshanov ◽  
Wlodek Kaplan ◽  
A. Zhang ◽  
Tomas Hjort ◽  
...  
Keyword(s):  
Leakage Current ◽  
Doping Concentration ◽  
Voltage Drop ◽  
Schottky Contact ◽  
Drift Region ◽  
Forward Voltage ◽  
Forward Voltage Drop ◽  
Increasing Temperature ◽  
P Type ◽  
State Resistance

4H-SiC Schottky Barrier Diodes (SBD) have been developed using p-type buried grids (BGs) formed by Al implantation. In order to reduce on-state resistance and improve forward conduction, the doping concentration of the channel region between the buried grids was increased. The fabricated diodes were encapsulated with TO-254 packages and electrically evaluated. Experimental forward and reverse characteristics were measured in the temperature range from 25 °C to 250 °C. On bare die level, the forward voltage drop was reduced from 5.36 V to 3.90 V at 20 A as the channel doping concentration was increased, which introduced a low channel resistance. By the encapsulation in TO-254 package, the forward voltage drop was decreased approximately 10% due to a lower contact resistance. The on-state resistance of the identical device measured on bare die and in TO-254 package increased with increasing temperature due to the decreased electron mobility in the drift region resulting in higher resistance. The incremental contact resistances of the bare dies were larger than in the packaged devices. One key issue associated with conventional Junction Barrier Schottky (JBS) diodes is a high leakage current at high temperature operation over 200 °C. The developed Buried Grid JBS (BG JBS) diode has significantly reduced leakage current due to a better field shielding at the Schottky contact. The leakage current of the packaged BG JBS diodes is compared to pure SBD and commercial JBS diodes.

10 kV, 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC

2010 ◽  
Vol 645-648 ◽  
pp. 1025-1028 ◽  
Author(s):  
Qing Chun Jon Zhang ◽  
Robert Callanan ◽  
Anant K. Agarwal ◽  
Albert A. Burk ◽  
Michael J. O'Loughlin ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Voltage Drop ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Collector Current ◽  
Forward Voltage ◽  
Collector Voltage ◽  
Forward Voltage Drop ◽  
Chip Size ◽  
Dc Current

4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.

High Voltage Silicon Carbide Devices

1998 ◽  
Vol 512 ◽  
Author(s):  
B. Jayant Baliga
Keyword(s):  
Silicon Carbide ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Impact Ionization ◽  
Voltage Drop ◽  
Schottky Diodes ◽  
Inversion Layer ◽  
Drift Region ◽  
Edge Termination ◽  
Silicon Devices

ABSTRACTProgress made in the development of high performance power rectifiers and switches from silicon carbide are reviewed with emphasis on approaching the 100-fold reduction in the specific on-resistance of the drift region when compared with silicon devices with the same breakdown voltage. The highlights are: (a) Recently completed measurements of impact ionization coefficients in SiC indicate an even higher Baliga's figure of merit than projected earlier. (b) The commonly reported negative temperature co-efficient for breakdown voltage in SiC devices has been shown to arise at defects, allaying concerns that this may be intrinsic to the material. (c) Based upon fundamental considerations, it has been found that Schottky rectifiers offer superior on-state voltage drop than P-i-N rectifiers for reverse blocking voltages below 3000 volts. (d) Nearly ideal breakdown voltage has been experimentally obtained for Schottky diodes using an argon implanted edge termination. (e) Planar ion-implanted junctions have been successfully fabricated using oxide as a mask with high breakdown voltage and low leakage currents by using a filed plate edge termination. (f) High inversion layer mobility has been experimentally demonstrated on both 6H and 4H-SiC by using a deposited oxide layer as gate dielectric. (g) A novel, high-voltage, normally-off, accumulation-channel, MOSFET has been proposed and demonstrated with 50x lower specific on-resistance than silicon devices in spite of using logic-level gate drive voltages. These results indicate that SiC based power devices could become commercially viable in the 21st century if cost barriers can be overcome.

Doping Concentration Optimization for Ultra-Low-Loss 4H-SiC Floating Junction Schottky Barrier Diode (Super-SBD)

2009 ◽  
Vol 615-617 ◽  
pp. 655-658 ◽  
Author(s):  
Chiharu Ota ◽  
Johji Nishio ◽  
Kazuto Takao ◽  
Tetsuo Hatakeyama ◽  
Takashi Shinohe ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Breakdown Voltage ◽  
Dynamic Characteristics ◽  
Figure Of Merit ◽  
Doping Concentration ◽  
Drift Region ◽  
Static Characteristics ◽  
Low Loss ◽  
Significant Lowering ◽  
Floating Layer

Previous simulation works and experiments on the loss of 4H-SiC floating junction Schottky barrier diodes (Super-SBDs) show that the loss is related to the doping concentration in the drift region and the pattern of the floating layer. The effect of the doping concentration for lowering the loss is characterized the breakdown voltage (Vbd) and the on-state resistances (RonS) of the Super-SBDs based on Baliga’s figure of Merit (BFOM). Experimental devices with two doping concentrations in the drift region are fabricated to investigate the static characteristics: Vbd and RonS. The Vbd of the Super-SBDs is close to the simulation result, near 3000 V. However the tendency of the Vbd by the doping concentration is not similar to the simulation result. And the RonS are about 3.22 mcm2 which is higher than that of simulation result. The doping concentration optimized in this study does not show significant lowering loss and the design of the floating layer in the termination region affect the low-loss static characteristics of the Super-SBD. In addition, adopting PiN structure with floating layer (Super-PiN) affects the low-loss dynamic characteristics, optimizing the doping concentration in the drift region. We conclude that the fabricated Super-SBDs with the floating layer in the termination region, the drift region with a doping concentration of 1.01016 cm-3 and mesa-shaped termination structure, have excellent Vbd of 2990 V which is almost same as that of simulation result and RonS of 3.22 mcm2.

scholarly journals A Novel LDMOS with Ultralow Specific on-Resistance and Improved Switching Performance

2021 ◽  
Author(s):  
Lijuan Wu ◽  
Haifeng Wu ◽  
Jinsheng Zeng ◽  
Xing Chen ◽  
Shaolian Su
Keyword(s):  
Breakdown Voltage ◽  
Current Distribution ◽  
Doping Concentration ◽  
Electric Field Distribution ◽  
Drift Region ◽  
Optimal Doping ◽  
Field Plate ◽  
Switching Performance ◽  
Switching Losses ◽  
Optimal Doping Concentration

Abstract A stepped split triple-gate SOI LDMOS with P/N strip (P/N SSTG SOI LDMOS) is proposed, which has ultralow specific on-resistance (Ron,sp) and low switching losses. The proposed device has a triple-gate (TG) and stepped split gates (SSGs). P strip, N-drift and oxide trench are alternately arranged in the Z direction. Meanwhile, the SSGs are located in the oxide trench of the N-drift region and are distributed in steps. Firstly, the TG increases the channel width (Wch) and has the effect of modulating current distribution, resulting in lower Ron,sp and higher transconductance (gm). Secondly, the SSGs serve as the field plate to assist the depletion of the N-drift region, increasing the optimal doping concentration of the N-drift region (Nd-opt) and further reducing the Ron,sp. Moreover, the SSGs also have the effect of modulating the electric field distribution to maintain a high breakdown voltage (BV). Meanwhile, gate-drain charge (QGD) and switching losses are reduced on account of the introduction of the SSGs. Thirdly, in the off-state, the P strip and SSGs multidimensional assisted depletion of the N-drift region, which greatly increases the Nd-opt. The highly doped N-drift region provides a low-resistance path for the current, which also further reduces Ron,sp. Compared with triple-gate (TG) SOI LDMOS with almost equal breakdown voltage, the Ron,sp and QGD of P/N SSTG SOI LDMOS are reduced by 62% and 63%, respectively.

The Impact of Schottky Barrier Tunneling on SiC-JBS Performance

2009 ◽  
Vol 615-617 ◽  
pp. 667-670 ◽  
Author(s):  
Gary M. Dolny ◽  
Richard L. Woodin ◽  
T. Witt ◽  
J. Shovlin
Keyword(s):  
Electric Field ◽  
Breakdown Voltage ◽  
Voltage Drop ◽  
Forward Voltage ◽  
Trade Off ◽  
Practical Applications ◽  
Forward Voltage Drop ◽  
Surface Electric Field ◽  
The Impact ◽  
Barrier Tunneling

The impact of barrier tunneling on SiC-JBS performance is studied both experimentally and theoretically. We show that although the pinch-off effects associated with the JBS structure can significantly suppress the surface electric field, barrier tunneling still dominates the reverse behavior. Barrier tunneling determines the apparent breakdown voltage, as well as the apparent breakdown voltage vs. forward voltage drop trade-off of the JBS diode in practical applications.

Influence of Trench Design on the Electrical Properties of 650V 4H-SiC JBS Diodes

2019 ◽  
Vol 963 ◽  
pp. 549-552
Author(s):  
Oleg Rusch ◽  
Jonathan Moult ◽  
Tobias Erlbacher
Keyword(s):  
Electrical Properties ◽  
Leakage Current ◽  
Breakdown Voltage ◽  
Voltage Drop ◽  
Electrical Characteristics ◽  
Electrical Field ◽  
Forward Voltage ◽  
Voltage Drops ◽  
Forward Voltage Drop ◽  
Trench Structure

This work presents a design study of customized p+ arrays having influence on the electrical properties of manufactured 4H-SiC Junction Barrier Schottky (JBS) diodes with designated electrical characteristics of 5 A forward and 650 V blocking capabilities. The effect of the Schottky area consuming p+ grid on the forward voltage drop, the leakage current and therefore the breakdown voltage was investigated. A recessed p+ implantation, realized through trench etching before implanting the bottom of the trenches, results in a more effective shielding of the electrical field at the Schottky interface and therefore reduces the leakage current. Customizing the p+ grid array in combination with the trench structure, various JBS diode variants with active areas of 1.69 mm2 were fabricated whereas forward voltage drops of 1.58 V @ 5 A with blocking capabilities up to 1 kV were achieved.

1200-V, 50-A, Silicon Carbide Vertical Junction Field Effect Transistors for Power Switching Applications

2008 ◽  
Vol 600-603 ◽  
pp. 1047-1050 ◽  
Author(s):  
Victor Veliadis ◽  
Ty McNutt ◽  
Megan McCoy ◽  
Harold Hearne ◽  
Gregory De Salvo ◽  
...  
Keyword(s):  
Voltage Drop ◽  
Field Effect Transistors ◽  
Ring Structure ◽  
Avalanche Breakdown ◽  
Guard Ring ◽  
Gate Bias ◽  
Drain Voltage ◽  
Power Switching ◽  
Gate Current ◽  
Voltage Limit

High-voltage normally-on VJFETs of 0.19 cm2 and 0.096 cm2 areas were manufactured in seven photolithographic levels with no epitaxial regrowth and a single ion implantation event. A self aligned guard ring structure provided edge termination. At a gate bias of -36 V the 0.096 cm2 VJFET blocks 1980 V, which corresponds to 91% of the 12 μm drift layer’s avalanche breakdown voltage limit. It outputs 25 A at a forward drain voltage drop of 2 V (368 A/cm2, 735 W/cm2) and a gate current of 4 mA. The specific on-resistance is 5.4 mΩ cm2. The 0.19 cm2 VJFET blocks 1200 V at a gate bias of -26 V. It outputs 54 A at a forward drain voltage drop of 2 V (378 A/cm2, 755 W/cm2) and a gate current of 12 mA, with a specific on-resistance of 5.6 mΩ cm2. The VJFETs demonstrated low gate-to-source leakage currents with sharp onsets of avalanche breakdown.

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