scholarly journals 150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 504
Author(s):  
Feng-Tso Chien ◽  
Zhi-Zhe Wang ◽  
Cheng-Li Lin ◽  
Tsung-Kuei Kang ◽  
Chii-Wen Chen ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Integrated System ◽  
Oxide Semiconductor ◽  
Epitaxial Layers ◽  
Engineering Technology ◽  
Power Mosfet ◽  
Power Mosfets ◽  
Aided Design ◽  
State Resistance

A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

scholarly journals Study of a SiC Trench MOSFET Edge-Termination Structure with a Bottom Protection Well for a High Breakdown Voltage

2020 ◽  
Vol 10 (3) ◽  
pp. 753
Author(s):  
Jee-Hun Jeong ◽  
Ju-Hong Cha ◽  
Goon-Ho Kim ◽  
Sung-Hwan Cho ◽  
Ho-Jun Lee
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Surface Region ◽  
Ring Structure ◽  
Oxide Semiconductor ◽  
Cross Sectional ◽  
Edge Termination ◽  
Additional Process ◽  
Aided Design ◽  
Sectional Structure

A novel edge-termination structure for a SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) power device is proposed. The key feature of the proposed structure is a periodically formed SiC trench with a bottom protection well (BPW) implantation region. The trench can be filled with oxide or gate materials. Indeed, it has almost the same cross-sectional structure as the active region of a SiC trench MOSFET. Therefore, there is little or no additional process loads. A conventional floating field ring (FFR) structure utilizes the spreading of the electric field in the periodically depleted surface region formed between a heavily doped equipotential region. On the other hand, in the trenched ring structure, an additional quasi-equipotential region is provided by the BPW region, which enables deeper and wider field-spreading profiles, and less field crowding at the edge region. The two-dimensional Technology Computer Aided Design (2D-TCAD) simulation results show that the proposed trenched ring-edge termination structures have an improved breakdown voltage compared to the conventional floating field ring structure.

scholarly journals New Power MOSFET with Beyond-1D-Limit RSP-BV Trade-Off and Superior Reverse Recovery Characteristics

Materials ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2581
Author(s):  
Meng Zhang ◽  
Baikui Li ◽  
Jin Wei
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Power Switching ◽  
Deep Trench ◽  
Trade Off ◽  
Power Mosfet ◽  
P Bodies ◽  
Recovery Performance

The application of conventional power metal-oxide-semiconductor field-effect transistor (MOSFET) is limited by the famous one-dimensional “silicon limit” (1D-limit) in the trade-off relationship between specific on-resistance (RSP) and breakdown voltage (BV). In this paper, a new power MOSFET architecture is proposed to achieve a beyond-1D-limit RSP-BV trade-off. Numerical TCAD (technology computer-aided design) simulations were carried out to comparatively study the proposed MOSFET, the conventional power MOSFET, and the superjunction MOSFET. All the devices were designed with the same breakdown voltage of ~550 V. The proposed MOSFET features a deep trench between neighboring p-bodies and multiple p-islands located at the sidewall and bottom of the trench. The proposed MOSFET allows a high doping concentration in the drift region, which significantly reduces its RSP compared to the conventional power MOSFET. The multiple p-islands split the electric field into multiple peaks and help the proposed MOSFET maintain a similar breakdown voltage to the conventional power MOSFET with the same drift region thickness. Another famous device technology, the superjunction MOSFET (SJ-MOSFET), also breaks the 1D-limit. However, the SJ-MOSFET suffers a snappy reverse recovery performance, which is a notorious drawback of SJ-MOSFET and limits the range of its application. On the contrary, the proposed MOSFET presents a superior reverse recovery performance and can be used in various power switching applications where hard commutation is required.

Automation of the technology of connecting parts in the manufacture of aerospace products

2021 ◽  
pp. 24-32
Author(s):  
S. I. Ponomarev
Keyword(s):  
Technological Process ◽  
Computer Aided Design ◽  
Mechanical Engineering ◽  
Experimental Studies ◽  
Diffusion Welding ◽  
Technological Equipment ◽  
State University ◽  
Engineering Technology ◽  
Heat Resistant ◽  
Aided Design

The paper describes the improvement of the technology of manufacturing parts and components of aerospace production using computer-aided design and technological process control. The theoretical foundations and algorithms for constructing the technological process of manufacturing parts and components of the aerospace industry using various methods of joining heat-resistant materials, for example, by diffusion welding, are designed on the basis of theoretical and experimental studies proposed by the author of the patented connection method «Method for joining a heat-resistant cobalt-based alloy with silicon nitride-based ceramics» and technological equipment «Installation for obtaining metal-ceramic products», as well as «Attribute database for creating technological processes for obtaining parts of aerospace production by diffusion welding» and «Attribute database of technological equipment, tools and devices for mechanical processing of aerospace production parts», registered in the register of databases of the Russian Federation. The research is conducted at the Department of Mechanical Engineering Technology of the Institute of Mechanical Engineering and Mechatronics of the Siberian State University of Science and Technology named after academician M.F. Reshetnev.

scholarly journals A New Split Gate Resurf Stepped Oxide UMOSFET Structure with High Doped Epitaxial Layer for Improving Figure of Merit (FOM)

2020 ◽  
Vol 10 (21) ◽  
pp. 7895
Author(s):  
Runze Chen ◽  
Lixin Wang ◽  
Hongkai Zhang ◽  
Mengyao Cui ◽  
Min Guo
Keyword(s):  
Electric Field ◽  
Epitaxial Layer ◽  
Computer Aided Design ◽  
Figure Of Merit ◽  
Cost Effective ◽  
Oxide Semiconductor ◽  
Fabrication Procedure ◽  
Conventional Structure ◽  
Aided Design ◽  
Reduced Surface

The split gate resurf stepped oxide with highly doped epitaxial layer (HDSGRSO) UMOSFET has been proposed. The epitaxial layer of HDSGRSO u-shape metal oxide semiconductor field effect transistor (UMOSFET) has been divided into three parts: the upper epitaxial layer, the lower epitaxial layer and the middle epitaxial layer with higher doping concentration. The research shows that the reduced SURface field (RESURF) active has been enhanced due to the high doped epitaxial layer, which can modulate the electric field distribution and reduce the internal high electric field. Therefore, the HDGRSO UMOSFET has a higher breakdown voltage (BV), a lower on-state specific resistance (RSP) and a better figure of merit (FOM). According to the results of Technology Computer Aided Design (TCAD) simulations, the FOM (BV2/RSP) of HDSGRSO UMOSFET has been improved by 464%, and FOM (RSP × Qgd) of HDSGRSO UMOSFET has been reduced by 27.9% compared to the conventional structure, respectively, when the BV is 240 V. Furthermore, there is no extra special process required in this advanced fabrication procedure, which is relatively cost-effective and achievable.

scholarly journals Device Design Assessment of GaN Merged P-i-N Schottky Diodes

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1550 ◽  
Author(s):  
Yuliang Zhang ◽  
Xing Lu ◽  
Xinbo Zou
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Schottky Diodes ◽  
Schottky Contact ◽  
Background Concentration ◽  
Model Parameters ◽  
Design Assessment ◽  
Blocking Voltage ◽  
Aided Design ◽  
Drift Layer

Device characteristics of GaN merged P-i-N Schottky (MPS) diodes were evaluated and studied via two-dimensional technology computer-aided design (TCAD) after calibrating model parameters and critical electrical fields with experimental proven results. The device’s physical dimensions and drift layer concentration were varied to study their influence on the device’s performance. Extending the inter-p-GaN region distance or the Schottky contact portion could enhance the forward conduction capability; however, this leads to compromised electrical field screening effects from neighboring PN junctions, as well as reduced breakdown voltage. By reducing the drift layer background concentration, a higher breakdown voltage was expected for MPSs, as a larger portion of the drift layer itself could be depleted for sustaining vertical reverse voltage. However, lowering the drift layer concentration would also result in a reduction in forward conduction capability. The method and results of this study provide a guideline for designing MPS diodes with target blocking voltage and forward conduction at a low bias.

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